ARM: Warn about and ignore accesses to DCCISW.

This register is supposed to "Clean and invalidate data or unified cache line
by set/way." Since there isn't a good way to do that, we'll just ignore these
and warn about it.

1 files changed, 3 insertions, 0 deletions

diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 897ecf3e3..5498a84b0 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -94,6 +94,9 @@ def format McrMrc15() {{
             return new NopInst(machInst);
         } else if (miscReg == NUM_MISCREGS) {
             return new Unknown(machInst);
+        } else if (miscReg == MISCREG_DCCISW) {
+            return new WarnUnimplemented(isRead ? "mrc dccisw" : "mcr dcisw",
+                                         machInst);
         } else {
             if (isRead) {
                 return new Mrc15(machInst, rt, (IntRegIndex)miscReg);