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| author | Ali Saidi <Ali.Saidi@arm.com> | 2010-08-23 11:18:40 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@arm.com> | 2010-08-23 11:18:40 -0500 |
| commit | 38cf6a164d7081f1a2f40ab210169681b4cd6929 (patch) | |
| tree | 98f3a6f7b4fdbb3f271f4a5b59302b85e6caa821 /src/arch/arm/isa/formats/misc.isa | |
| parent | b7b2eae6fa56a5b2923f8aa8cd7b5425d10163df (diff) | |
| download | gem5-38cf6a164d7081f1a2f40ab210169681b4cd6929.tar.xz | |
ARM: Implement some more misc registers
Diffstat (limited to 'src/arch/arm/isa/formats/misc.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 2801ebedf..884d93066 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -113,6 +113,9 @@ let {{ case MISCREG_DCCMVAC: return new WarnUnimplemented( isRead ? "mrc dccmvac" : "mcr dccmvac", machInst); + case MISCREG_DCCMVAU: + return new WarnUnimplemented( + isRead ? "mrc dccmvau" : "mcr dccmvau", machInst); case MISCREG_CP15ISB: return new WarnUnimplemented( isRead ? "mrc cp15isb" : "mcr cp15isb", machInst); |