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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-15 14:04:04 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-15 14:04:04 -0600 |
| commit | 4a1814bd524e7444f57dcd1ea24070fd7b375af3 (patch) | |
| tree | ffab2e2662c660ecd8905efbbf98efafb1ddd2ec /src/arch/arm/isa/formats/misc.isa | |
| parent | d4767f440a7a8bfefa0851726b729b8d30a654a5 (diff) | |
| download | gem5-4a1814bd524e7444f57dcd1ea24070fd7b375af3.tar.xz | |
ARM: Return an FailUnimp instruction when an unimplemented CP15 register is accessed.
Just panicing in readMiscReg() doesn't work because a speculative access
in the o3 model can end the simulation.
Diffstat (limited to 'src/arch/arm/isa/formats/misc.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 2d47c286f..c2003fe6d 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -180,6 +180,10 @@ let {{ // Read/write, priveleged only. default: + if (miscReg >= MISCREG_CP15_UNIMP_START) + return new FailUnimplemented(csprintf("%s %s", + isRead ? "mrc" : "mcr", miscRegName[miscReg]).c_str(), + machInst); if (isRead) { return new Mrc15(machInst, rt, (IntRegIndex)miscReg); } else { |