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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-02-23 15:10:49 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-02-23 15:10:49 -0600 |
| commit | 7391ea6de63578722d97c9169e60db5b06754137 (patch) | |
| tree | c544188de95cc72b74467bdec048883f300a5b61 /src/arch/arm/isa/formats/misc.isa | |
| parent | ae3d45685512b75f878eb9d7917680fc3971988e (diff) | |
| download | gem5-7391ea6de63578722d97c9169e60db5b06754137.tar.xz | |
ARM: Do something for ISB, DSB, DMB
Diffstat (limited to 'src/arch/arm/isa/formats/misc.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 3bcb5c97d..4a9200504 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -120,14 +120,11 @@ let {{ return new WarnUnimplemented( isRead ? "mrc dccmvau" : "mcr dccmvau", machInst); case MISCREG_CP15ISB: - return new WarnUnimplemented( - isRead ? "mrc cp15isb" : "mcr cp15isb", machInst); + return new Isb(machInst); case MISCREG_CP15DSB: - return new WarnUnimplemented( - isRead ? "mrc cp15dsb" : "mcr cp15dsb", machInst); + return new Dsb(machInst); case MISCREG_CP15DMB: - return new WarnUnimplemented( - isRead ? "mrc cp15dmb" : "mcr cp15dmb", machInst); + return new Dmb(machInst); case MISCREG_ICIALLUIS: return new WarnUnimplemented( isRead ? "mrc icialluis" : "mcr icialluis", machInst); |