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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:09 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:09 -0500
commit741b24326040cfdd534d05ca46ba4c962bab18f1 (patch)
tree9f5e3279e7c0fbc1114a0fd410281f95d8356a3e /src/arch/arm/isa/formats/misc.isa
parent8a7f60194ea24f63759d1985cc04c1fa8b8e2dcb (diff)
downloadgem5-741b24326040cfdd534d05ca46ba4c962bab18f1.tar.xz
ARM: Ignore/warn access to the bpimva registers.
Diffstat (limited to 'src/arch/arm/isa/formats/misc.isa')
-rw-r--r--src/arch/arm/isa/formats/misc.isa3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 8ba46960a..7d58350a4 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -119,6 +119,9 @@ def format McrMrc15() {{
case MISCREG_ICIMVAU:
return new WarnUnimplemented(
isRead ? "mrc icimvau" : "mcr icimvau", machInst);
+ case MISCREG_BPIMVA:
+ return new WarnUnimplemented(
+ isRead ? "mrc bpimva" : "mcr bpimva", machInst);
default:
if (isRead) {
return new Mrc15(machInst, rt, (IntRegIndex)miscReg);