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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:08 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:08 -0500 |
| commit | 7932b862986c325d647097e13ffb6a54a5cc93b9 (patch) | |
| tree | db2903a45b5c3f9f391383dac5a1a858fc2e3a40 /src/arch/arm/isa/formats/misc.isa | |
| parent | 6ae4d34a124b0c06a30c7ddb9da6d59225aa6cf3 (diff) | |
| download | gem5-7932b862986c325d647097e13ffb6a54a5cc93b9.tar.xz | |
ARM: Ignore accesses to DCCIMVAC.
Diffstat (limited to 'src/arch/arm/isa/formats/misc.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 5498a84b0..74e10a2d8 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -90,14 +90,18 @@ def format McrMrc15() {{ const bool isRead = bits(machInst, 20); - if (miscReg == MISCREG_NOP) { + switch (miscReg) { + case MISCREG_NOP: return new NopInst(machInst); - } else if (miscReg == NUM_MISCREGS) { + case NUM_MISCREGS: return new Unknown(machInst); - } else if (miscReg == MISCREG_DCCISW) { - return new WarnUnimplemented(isRead ? "mrc dccisw" : "mcr dcisw", - machInst); - } else { + case MISCREG_DCCISW: + return new WarnUnimplemented( + isRead ? "mrc dccisw" : "mcr dcisw", machInst); + case MISCREG_DCCIMVAC: + return new WarnUnimplemented( + isRead ? "mrc dccimvac" : "mcr dcimvac", machInst); + default: if (isRead) { return new Mrc15(machInst, rt, (IntRegIndex)miscReg); } else { |