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| author | Chander Sudanthi <Chander.Sudanthi@ARM.com> | 2011-09-13 12:06:13 -0500 |
|---|---|---|
| committer | Chander Sudanthi <Chander.Sudanthi@ARM.com> | 2011-09-13 12:06:13 -0500 |
| commit | 7c479d734922d0b9dd5c9b4404ef6d62b3d91075 (patch) | |
| tree | 769ca64c18b45fb6505d24233a601c879778ecd2 /src/arch/arm/isa/formats/misc.isa | |
| parent | 09a6e424ec966d66ec2f8cfba86d4b4141438c5a (diff) | |
| download | gem5-7c479d734922d0b9dd5c9b4404ef6d62b3d91075.tar.xz | |
CP15 c15: enable execution with accesses to c15 registers
Previously, coprocessor accesses to CP15 c15 would fault. This patch
enables accesses but prints out a warning, as the registers are not implemented.
Diffstat (limited to 'src/arch/arm/isa/formats/misc.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 4a9200504..54482864a 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -143,6 +143,9 @@ let {{ case MISCREG_L2LATENCY: return new WarnUnimplemented( isRead ? "mrc l2latency" : "mcr l2latency", machInst); + case MISCREG_CRN15: + return new WarnUnimplemented( + isRead ? "mrc crn15" : "mcr crn15", machInst); // Write only. case MISCREG_TLBIALLIS: |