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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:09 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:09 -0500
commit896c7617c47cd83b0e119b62baa133307d05cecd (patch)
tree9e80ad96c19a94c5194d0661bbc18f8bf52ca5c2 /src/arch/arm/isa/formats/misc.isa
parentaf6b1667e947ec801cbc4568f8ca060ebc976dcd (diff)
downloadgem5-896c7617c47cd83b0e119b62baa133307d05cecd.tar.xz
ARM: Decode the unimplemented data barrier CP15 accesses.
These are CP15DSB (Data Synchronization Barrier), and CP15DMB (Data Memory Barrier).
Diffstat (limited to 'src/arch/arm/isa/formats/misc.isa')
-rw-r--r--src/arch/arm/isa/formats/misc.isa6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index ace90786f..e966fe423 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -104,6 +104,12 @@ def format McrMrc15() {{
case MISCREG_CP15ISB:
return new WarnUnimplemented(
isRead ? "mrc cp15isb" : "mcr cp15isb", machInst);
+ case MISCREG_CP15DSB:
+ return new WarnUnimplemented(
+ isRead ? "mrc cp15dsb" : "mcr cp15dsb", machInst);
+ case MISCREG_CP15DMB:
+ return new WarnUnimplemented(
+ isRead ? "mrc cp15dmb" : "mcr cp15dmb", machInst);
default:
if (isRead) {
return new Mrc15(machInst, rt, (IntRegIndex)miscReg);