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| author | Min Kyu Jeong <minkyu.jeong@arm.com> | 2010-08-25 19:10:43 -0500 |
|---|---|---|
| committer | Min Kyu Jeong <minkyu.jeong@arm.com> | 2010-08-25 19:10:43 -0500 |
| commit | c23e8c31ebd4e856f205f5bdd8f4eb5e1eec87ee (patch) | |
| tree | a04e718c24dc0d40829342042fba144b187fd1bb /src/arch/arm/isa/formats/misc.isa | |
| parent | 8376f7bca3814844ab9cc592ff8f32c702a18629 (diff) | |
| download | gem5-c23e8c31ebd4e856f205f5bdd8f4eb5e1eec87ee.tar.xz | |
ARM: Adding a bogus fault that does nothing.
This fault can used to flush the pipe, not including the faulting instruction.
The particular case I needed this was for a self-modifying code. It needed to
drain the store queue and force the following instruction to refetch from
icache. DCCMVAC cp15 mcr instruction is modified to raise this fault.
Diffstat (limited to 'src/arch/arm/isa/formats/misc.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 884d93066..2d47c286f 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -111,7 +111,7 @@ let {{ return new WarnUnimplemented( isRead ? "mrc dcimvac" : "mcr dcimvac", machInst); case MISCREG_DCCMVAC: - return new WarnUnimplemented( + return new FlushPipeInst( isRead ? "mrc dccmvac" : "mcr dccmvac", machInst); case MISCREG_DCCMVAU: return new WarnUnimplemented( |