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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:13 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:13 -0500 |
| commit | e21f93702ab8d03a8eddffc1a7b33f51af82e8c2 (patch) | |
| tree | 6e6d6e5a86156dca91f33cca7bd67a8902601a46 /src/arch/arm/isa/formats/misc.isa | |
| parent | eac239b4d6f6d9eccb3837330e3f22acefc1b48e (diff) | |
| download | gem5-e21f93702ab8d03a8eddffc1a7b33f51af82e8c2.tar.xz | |
ARM: Warn/ignore when TLB maintenance operations are performed.
Diffstat (limited to 'src/arch/arm/isa/formats/misc.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 8d386b0b0..9ce199637 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -128,6 +128,48 @@ def format McrMrc15() {{ case MISCREG_BPIALL: return new WarnUnimplemented( isRead ? "mrc bpiall" : "mcr bpiall", machInst); + case MISCREG_TLBIALLIS: + return new WarnUnimplemented( + isRead ? "mrc tlbiallis" : "mcr tlbiallis", machInst); + case MISCREG_TLBIMVAIS: + return new WarnUnimplemented( + isRead ? "mrc tlbimvais" : "mcr tlbimvais", machInst); + case MISCREG_TLBIASIDIS: + return new WarnUnimplemented( + isRead ? "mrc tlbiasidis" : "mcr tlbiasidis", machInst); + case MISCREG_TLBIMVAAIS: + return new WarnUnimplemented( + isRead ? "mrc tlbimvaais" : "mcr tlbimvaais", machInst); + case MISCREG_ITLBIALL: + return new WarnUnimplemented( + isRead ? "mrc itlbiall" : "mcr itlbiall", machInst); + case MISCREG_ITLBIMVA: + return new WarnUnimplemented( + isRead ? "mrc itlbimva" : "mcr itlbimva", machInst); + case MISCREG_ITLBIASID: + return new WarnUnimplemented( + isRead ? "mrc itlbiasid" : "mcr itlbiasid", machInst); + case MISCREG_DTLBIALL: + return new WarnUnimplemented( + isRead ? "mrc dtlbiall" : "mcr dtlbiall", machInst); + case MISCREG_DTLBIMVA: + return new WarnUnimplemented( + isRead ? "mrc dtlbimva" : "mcr dtlbimva", machInst); + case MISCREG_DTLBIASID: + return new WarnUnimplemented( + isRead ? "mrc dtlbiasid" : "mcr dtlbiasid", machInst); + case MISCREG_TLBIALL: + return new WarnUnimplemented( + isRead ? "mrc tlbiall" : "mcr tlbiall", machInst); + case MISCREG_TLBIMVA: + return new WarnUnimplemented( + isRead ? "mrc tlbimva" : "mcr tlbimva", machInst); + case MISCREG_TLBIASID: + return new WarnUnimplemented( + isRead ? "mrc tlbiasid" : "mcr tlbiasid", machInst); + case MISCREG_TLBIMVAA: + return new WarnUnimplemented( + isRead ? "mrc tlbimvaa" : "mcr tlbimvaa", machInst); default: if (isRead) { return new Mrc15(machInst, rt, (IntRegIndex)miscReg); |