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| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-02-07 11:35:10 +0000 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-12-05 11:47:01 +0000 |
| commit | eeb36e5b6e81c6b9ea6a0c3c97573e762e58ae05 (patch) | |
| tree | 9ea079dc4bc5b04cfc4b84a32c06225670be69dd /src/arch/arm/isa/formats/misc.isa | |
| parent | b9edb351454c2601070fb9432f23fc3914eb33c1 (diff) | |
| download | gem5-eeb36e5b6e81c6b9ea6a0c3c97573e762e58ae05.tar.xz | |
arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructions
This patch adds support for the ARMv7 cache maintenance
intructions:
* mcr dccmvac cleans a VA to the PoC
* mcr dcimvac invalidates a VA to the PoC
* mcr dccimvac cleans and invalidates a VA to the PoC
* mcr dccmvau cleans a VA to the PoU
Change-Id: I6511f203039ca145cc9128ddf61d09d6d7e40c10
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5059
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/arm/isa/formats/misc.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 26681e40f..4f834b8e1 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010-2013,2016 ARM Limited +// Copyright (c) 2010-2013,2016-2017 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -219,15 +219,20 @@ let {{ machInst, csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown", crn, opc1, crm, opc2, isRead ? "read" : "write")); - case MISCREG_DCCMVAC: - return new McrMrcMiscInst(isRead ? "mrc dccmvac" : "mcr dccmvac", - machInst, iss, MISCREG_DCCMVAC); case MISCREG_CP15ISB: return new Isb(machInst, iss); case MISCREG_CP15DSB: return new Dsb(machInst, iss); case MISCREG_CP15DMB: return new Dmb(machInst, iss); + case MISCREG_DCIMVAC: + return new McrDcimvac(machInst, miscReg, rt, iss); + case MISCREG_DCCMVAC: + return new McrDccmvac(machInst, miscReg, rt, iss); + case MISCREG_DCCMVAU: + return new McrDccmvau(machInst, miscReg, rt, iss); + case MISCREG_DCCIMVAC: + return new McrDccimvac(machInst, miscReg, rt, iss); default: if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { std::string full_mnem = csprintf("%s %s", |