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authorGiacomo Travaglini <giacomo.travaglini@arm.com>2017-10-13 10:03:14 +0100
committerAndreas Sandberg <andreas.sandberg@arm.com>2017-11-15 14:11:44 +0000
commitef0490081fa7ebcda2e1c7adccb05b3a14014cf1 (patch)
tree8073449559fecaf9bc1fb8f280a50a30a9313863 /src/arch/arm/isa/formats/misc.isa
parentf0f04ddd70aa3260f5282227de264653ac36fabe (diff)
downloadgem5-ef0490081fa7ebcda2e1c7adccb05b3a14014cf1.tar.xz
arm: Add support for armv8 CRC32 instructions
This patch introduces the ARM A32/T32/A64 CRC Instructions, which are mandatory since ARMv8.1. The UNPREDICTABLE behaviours are implemented as follows: 1) CRC32(C)X (64 bit) instructions are decoded as Undefined in Aarch32 2) The instructions support predication in Aarch32 3) Using R15(PC) as source/dest operand is permitted in Aarch32 Change-Id: Iaf29b05874e1370c7615da79a07f111ded17b6cc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5521 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/formats/misc.isa')
-rw-r--r--src/arch/arm/isa/formats/misc.isa31
1 files changed, 31 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 43a7cc975..26681e40f 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -38,6 +38,37 @@
// Authors: Gabe Black
// Giacomo Gabrielli
+def format Crc32() {{
+ decode_block = '''
+ {
+ const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
+ const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+
+ uint8_t c_poly = bits(machInst, 9);
+ uint8_t sz = bits(machInst, 22, 21);
+ uint8_t crc_select = (c_poly << 2) | sz;
+
+ switch(crc_select) {
+ case 0x0:
+ return new Crc32b(machInst, rd, rn, rm);
+ case 0x1:
+ return new Crc32h(machInst, rd, rn, rm);
+ case 0x2:
+ return new Crc32w(machInst, rd, rn, rm);
+ case 0x4:
+ return new Crc32cb(machInst, rd, rn, rm);
+ case 0x5:
+ return new Crc32ch(machInst, rd, rn, rm);
+ case 0x6:
+ return new Crc32cw(machInst, rd, rn, rm);
+ default:
+ return new Unknown(machInst);
+ }
+ }
+ '''
+}};
+
def format ArmERet() {{
decode_block = "return new Eret(machInst);"
}};