diff options
author | Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com> | 2018-02-20 00:32:37 +0530 |
---|---|---|
committer | Gabe Black <gabeblack@google.com> | 2018-03-15 23:24:51 +0000 |
commit | 9dc44b4173b72d15fa7ee49d1b196c2d11c84d02 (patch) | |
tree | a55560518cf4395d1eab583cbeb51d6c06b28dbd /src/arch/arm/isa/formats/mult.isa | |
parent | 5a1e52d5a019c128c4c87783f76f4742c5e4455f (diff) | |
download | gem5-9dc44b4173b72d15fa7ee49d1b196c2d11c84d02.tar.xz |
arm: Fix implicit-fallthrough warnings when building with gcc-7+
gcc 7 onwards have additional heuristics to detect implicit
fallthroughs and it fails the build with warnings for ARM as a result.
There was one gcc bug[1] that I fixed but the rest are cases that gcc
cannot detect due to the point at which it does the fallthrough check.
Most of this patch adds __builtin_unreachable() hints in places that throw
this warning to indicate to gcc that the fallthrough will never
happen.
The remaining cases are actually possible fallthroughs due to
incorrect code running on the simulator; in which case an Unknown
instruction is returned.
[1] https://gcc.gnu.org/ml/gcc-patches/2018-02/msg01105.html
Change-Id: I1baa9fa0ed15181c10c755c0bd777f88b607c158
Signed-off-by: Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/8541
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/arch/arm/isa/formats/mult.isa')
-rw-r--r-- | src/arch/arm/isa/formats/mult.isa | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/mult.isa b/src/arch/arm/isa/formats/mult.isa index 73157dd57..142bfd67c 100644 --- a/src/arch/arm/isa/formats/mult.isa +++ b/src/arch/arm/isa/formats/mult.isa @@ -87,6 +87,8 @@ def format ArmMultAndMultAcc() {{ } else { return new Smlal(machInst, ra, rd, rn, rm); } + default: + M5_UNREACHABLE; } } ''' @@ -112,6 +114,8 @@ def format ArmHalfWordMultAndMultAcc() {{ return new SmlabtCc(machInst, rd, rn, rm, ra); case 0x3: return new SmlattCc(machInst, rd, rn, rm, ra); + default: + M5_UNREACHABLE; } case 0x1: if (op) { @@ -137,6 +141,8 @@ def format ArmHalfWordMultAndMultAcc() {{ return new Smlalbt(machInst, ra, rd, rn, rm); case 0x3: return new Smlaltt(machInst, ra, rd, rn, rm); + default: + M5_UNREACHABLE; } case 0x3: switch (bits(machInst, 6, 5)) { @@ -148,7 +154,11 @@ def format ArmHalfWordMultAndMultAcc() {{ return new Smulbt(machInst, rd, rn, rm); case 0x3: return new Smultt(machInst, rd, rn, rm); + default: + M5_UNREACHABLE; } + default: + M5_UNREACHABLE; } } ''' @@ -201,6 +211,7 @@ def format Thumb32MulMulAccAndAbsDiff() {{ return new SmlattCc(machInst, rd, rn, rm, ra); } } + M5_UNREACHABLE; case 0x2: if (ra == 0xf) { if (bits(machInst, 4)) { @@ -271,6 +282,8 @@ def format Thumb32MulMulAccAndAbsDiff() {{ } else { return new Usada8(machInst, rd, rn, rm, ra); } + default: + M5_UNREACHABLE; } } ''' |