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author | Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com> | 2018-02-20 00:32:37 +0530 |
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committer | Gabe Black <gabeblack@google.com> | 2018-03-15 23:24:51 +0000 |
commit | 9dc44b4173b72d15fa7ee49d1b196c2d11c84d02 (patch) | |
tree | a55560518cf4395d1eab583cbeb51d6c06b28dbd /src/arch/arm/isa/formats/neon64.isa | |
parent | 5a1e52d5a019c128c4c87783f76f4742c5e4455f (diff) | |
download | gem5-9dc44b4173b72d15fa7ee49d1b196c2d11c84d02.tar.xz |
arm: Fix implicit-fallthrough warnings when building with gcc-7+
gcc 7 onwards have additional heuristics to detect implicit
fallthroughs and it fails the build with warnings for ARM as a result.
There was one gcc bug[1] that I fixed but the rest are cases that gcc
cannot detect due to the point at which it does the fallthrough check.
Most of this patch adds __builtin_unreachable() hints in places that throw
this warning to indicate to gcc that the fallthrough will never
happen.
The remaining cases are actually possible fallthroughs due to
incorrect code running on the simulator; in which case an Unknown
instruction is returned.
[1] https://gcc.gnu.org/ml/gcc-patches/2018-02/msg01105.html
Change-Id: I1baa9fa0ed15181c10c755c0bd777f88b607c158
Signed-off-by: Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/8541
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/arch/arm/isa/formats/neon64.isa')
-rw-r--r-- | src/arch/arm/isa/formats/neon64.isa | 64 |
1 files changed, 34 insertions, 30 deletions
diff --git a/src/arch/arm/isa/formats/neon64.isa b/src/arch/arm/isa/formats/neon64.isa index e0a913a6b..b4d4fdf7b 100644 --- a/src/arch/arm/isa/formats/neon64.isa +++ b/src/arch/arm/isa/formats/neon64.isa @@ -181,6 +181,8 @@ namespace Aarch64 else return new OrnDX<uint64_t>(machInst, vd, vn, vm); } + default: + M5_UNREACHABLE; } case 0x04: if (size == 0x3) @@ -1211,6 +1213,8 @@ namespace Aarch64 return new DupGprXQX<uint64_t>(machInst, vd, vn); else return new Unknown64(machInst); + default: + return new Unknown64(machInst); } case 0x3: index1 = imm5 >> (imm5_pos + 1); @@ -2065,17 +2069,17 @@ namespace Aarch64 return decodeNeonUTwoMiscScFpReg<FcmltZeroScX>( size & 0x1, machInst, vd, vn); case 0x14: - if (size == 0x3) { + switch (size) { + case 0x0: + return new SqxtnScX<int8_t>(machInst, vd, vn); + case 0x1: + return new SqxtnScX<int16_t>(machInst, vd, vn); + case 0x2: + return new SqxtnScX<int32_t>(machInst, vd, vn); + case 0x3: return new Unknown64(machInst); - } else { - switch (size) { - case 0x0: - return new SqxtnScX<int8_t>(machInst, vd, vn); - case 0x1: - return new SqxtnScX<int16_t>(machInst, vd, vn); - case 0x2: - return new SqxtnScX<int32_t>(machInst, vd, vn); - } + default: + M5_UNREACHABLE; } case 0x1a: if (size < 0x2) @@ -2145,30 +2149,30 @@ namespace Aarch64 return decodeNeonUTwoMiscScFpReg<FcmleZeroScX>( size & 0x1, machInst, vd, vn); case 0x32: - if (size == 0x3) { + switch (size) { + case 0x0: + return new SqxtunScX<int8_t>(machInst, vd, vn); + case 0x1: + return new SqxtunScX<int16_t>(machInst, vd, vn); + case 0x2: + return new SqxtunScX<int32_t>(machInst, vd, vn); + case 0x3: return new Unknown64(machInst); - } else { - switch (size) { - case 0x0: - return new SqxtunScX<int8_t>(machInst, vd, vn); - case 0x1: - return new SqxtunScX<int16_t>(machInst, vd, vn); - case 0x2: - return new SqxtunScX<int32_t>(machInst, vd, vn); - } + default: + M5_UNREACHABLE; } case 0x34: - if (size == 0x3) { + switch (size) { + case 0x0: + return new UqxtnScX<uint8_t>(machInst, vd, vn); + case 0x1: + return new UqxtnScX<uint16_t>(machInst, vd, vn); + case 0x2: + return new UqxtnScX<uint32_t>(machInst, vd, vn); + case 0x3: return new Unknown64(machInst); - } else { - switch (size) { - case 0x0: - return new UqxtnScX<uint8_t>(machInst, vd, vn); - case 0x1: - return new UqxtnScX<uint16_t>(machInst, vd, vn); - case 0x2: - return new UqxtnScX<uint32_t>(machInst, vd, vn); - } + default: + M5_UNREACHABLE; } case 0x36: if (size != 0x1) { |