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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-01 22:16:19 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-01 22:16:19 -0700 |
| commit | f5141c23fd63c0fd89828ebf91317b1bd7f77881 (patch) | |
| tree | 96d28d6040f587dde648f6f6d85eb9c0111d7d5e /src/arch/arm/isa/formats/pred.isa | |
| parent | 22a1ac22f4015bb3fd6450c2643d647d5df97db8 (diff) | |
| download | gem5-f5141c23fd63c0fd89828ebf91317b1bd7f77881.tar.xz | |
ARM: Add defaults for DataOp flag code.
Diffstat (limited to 'src/arch/arm/isa/formats/pred.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/pred.isa | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa index dc115f588..0aada7bba 100644 --- a/src/arch/arm/isa/formats/pred.isa +++ b/src/arch/arm/isa/formats/pred.isa @@ -101,13 +101,24 @@ let {{ }}; -def format DataOp(code, icValue, ivValue) {{ +def format DataOp(code, icValue = {{ }}, + ivValue = {{ Cpsr<28:> }}) {{ regCode = '''uint32_t op2 = shift_rm_rs(Rm, Rs, shift, Cpsr<29:0>); op2 = op2;''' + code immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size, shift, Cpsr<29:0>); op2 = op2;''' + code + if icValue == " ": + icValueReg = 'shift_carry_rs(Rm, Rs, shift, Cpsr<29:>)' + icValueImm = 'shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)' + else: + icValueReg = icValue + icValueImm = icValue + regCcCode = calcCcCode % {"icValue" : icValueReg, + "ivValue" : ivValue} + immCcCode = calcCcCode % {"icValue" : icValueImm, + "ivValue" : ivValue} regIop = InstObjParams(name, Name, 'PredIntOp', {"code": regCode, "predicate_test": predicateTest}) @@ -115,10 +126,10 @@ def format DataOp(code, icValue, ivValue) {{ {"code": immCode, "predicate_test": predicateTest}) regCcIop = InstObjParams(name, Name + "Cc", 'PredIntOp', - {"code": regCode + calcCcCode % vars(), + {"code": regCode + regCcCode, "predicate_test": predicateTest}) immCcIop = InstObjParams(name, Name + "ImmCc", 'PredIntOp', - {"code": immCode + calcCcCode % vars(), + {"code": immCode + immCcCode, "predicate_test": predicateTest}) header_output = BasicDeclare.subst(regIop) + \ BasicDeclare.subst(immIop) + \ @@ -135,7 +146,9 @@ def format DataOp(code, icValue, ivValue) {{ decode_block = DataDecode.subst(regIop) }}; -def format DataImmOp(code, icValue, ivValue) {{ +def format DataImmOp(code, + icValue = {{ (rotate ? rotated_carry:Cpsr<29:>) }}, + ivValue = {{ Cpsr<28:> }}) {{ code += "resTemp = resTemp;" iop = InstObjParams(name, Name, 'PredImmOp', {"code": code, |