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| author | Gene Wu <Gene.Wu@arm.com> | 2010-08-23 11:18:41 -0500 |
|---|---|---|
| committer | Gene Wu <Gene.Wu@arm.com> | 2010-08-23 11:18:41 -0500 |
| commit | 66bcbec96e9bb9619b306a281cb18e2b4cea91c5 (patch) | |
| tree | 7cd3bdd69fb3fd19c59bcb1879491334be421d41 /src/arch/arm/isa/formats/uncond.isa | |
| parent | ad2c3b008dbc0496bdf4d80c93275e0bbebbb4fb (diff) | |
| download | gem5-66bcbec96e9bb9619b306a281cb18e2b4cea91c5.tar.xz | |
ARM: BX instruction can be contitional if last instruction in a IT block
Branches are allowed to be the last instuction in an IT block. Before it was
assumed that they could not. So Branches in thumb2 were Uncond.
Diffstat (limited to 'src/arch/arm/isa/formats/uncond.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/uncond.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/formats/uncond.isa b/src/arch/arm/isa/formats/uncond.isa index 4fa707b2b..079b472f3 100644 --- a/src/arch/arm/isa/formats/uncond.isa +++ b/src/arch/arm/isa/formats/uncond.isa @@ -231,7 +231,7 @@ def format ArmUnconditional() {{ const uint32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) | (bits(machInst, 24) << 1); - return new BlxImm(machInst, imm); + return new BlxImm(machInst, imm, COND_UC); } case 0x2: if (bits(op1, 4, 0) != 0) { |