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authorGene Wu <Gene.Wu@arm.com>2010-08-23 11:18:41 -0500
committerGene Wu <Gene.Wu@arm.com>2010-08-23 11:18:41 -0500
commit1f032ad3452c2514287c142fb3faf953a5682ea3 (patch)
treec37398638ecd1fcc43cb22c9c87f0384d7928127 /src/arch/arm/isa/formats/uncond.isa
parent66bcbec96e9bb9619b306a281cb18e2b4cea91c5 (diff)
downloadgem5-1f032ad3452c2514287c142fb3faf953a5682ea3.tar.xz
ARM: Implement CLREX
Diffstat (limited to 'src/arch/arm/isa/formats/uncond.isa')
-rw-r--r--src/arch/arm/isa/formats/uncond.isa2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/formats/uncond.isa b/src/arch/arm/isa/formats/uncond.isa
index 079b472f3..92e4db22d 100644
--- a/src/arch/arm/isa/formats/uncond.isa
+++ b/src/arch/arm/isa/formats/uncond.isa
@@ -97,7 +97,7 @@ def format ArmUnconditional() {{
} else if (op1 == 0x57) {
switch (op2) {
case 0x1:
- return new WarnUnimplemented("clrex", machInst);
+ return new Clrex(machInst);
case 0x4:
return new WarnUnimplemented("dsb", machInst);
case 0x5: