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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:13 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:13 -0500 |
| commit | 5d9191a428ee28b45a0f56e69e2f453a1fc21e73 (patch) | |
| tree | 2c8f50c29469a9db8cdef41e6483dc41b226467a /src/arch/arm/isa/formats/uncond.isa | |
| parent | 81b7c3d264c4caa366bd16aa644e72cad905e981 (diff) | |
| download | gem5-5d9191a428ee28b45a0f56e69e2f453a1fc21e73.tar.xz | |
ARM: Decode the unconditional version of ARM fp instructions.
Diffstat (limited to 'src/arch/arm/isa/formats/uncond.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/uncond.isa | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/uncond.isa b/src/arch/arm/isa/formats/uncond.isa index 0aa57a261..f1bfceac1 100644 --- a/src/arch/arm/isa/formats/uncond.isa +++ b/src/arch/arm/isa/formats/uncond.isa @@ -235,6 +235,9 @@ def format ArmUnconditional() {{ return new BlxImm(machInst, imm); } case 0x2: + if (CPNUM == 0xa || CPNUM == 0xb) { + return decodeExtensionRegLoadStore(machInst); + } if (bits(op1, 0) == 1) { if (rn == INTREG_PC) { if (bits(op1, 4, 3) != 0x0) { @@ -260,6 +263,9 @@ def format ArmUnconditional() {{ break; case 0x3: { + if (CPNUM == 0xa || CPNUM == 0xb) { + return decodeShortFpTransfer(machInst); + } const bool op = bits(machInst, 4); if (op) { if (bits(op1, 0)) { |