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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:11 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:11 -0500 |
| commit | 6fa713a66c380f38297e2306ec3d67e5fbb6f6c2 (patch) | |
| tree | 5ac07cc9154dafe155b2ee967338d2cc05ba21b1 /src/arch/arm/isa/formats/uncond.isa | |
| parent | 4683cd165575d6e1c5a309f10a96f4d592d7a386 (diff) | |
| download | gem5-6fa713a66c380f38297e2306ec3d67e5fbb6f6c2.tar.xz | |
ARM: Decode the setend instruction.
Diffstat (limited to 'src/arch/arm/isa/formats/uncond.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/uncond.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/formats/uncond.isa b/src/arch/arm/isa/formats/uncond.isa index d305ee996..fd2f66e75 100644 --- a/src/arch/arm/isa/formats/uncond.isa +++ b/src/arch/arm/isa/formats/uncond.isa @@ -44,7 +44,7 @@ def format ArmUnconditional() {{ const uint32_t op2 = bits(machInst, 7, 4); if (op1 == 0x10) { if (bits((uint32_t)rn, 0) == 1 && op2 == 0) { - return new WarnUnimplemented("setend", machInst); + return new Setend(machInst, bits(machInst, 9)); } else if (bits((uint32_t)rn, 0) == 0 && bits(op2, 1) == 0) { return new WarnUnimplemented("cps", machInst); } |