diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:11 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:11 -0500 |
| commit | ba33db8fd66fe0814a59d520df54f0bb3788ce1d (patch) | |
| tree | 404dbb98f0105abb8f4a30e563c25b37e0596312 /src/arch/arm/isa/formats/uncond.isa | |
| parent | 7861b084f6f800ebb1c8f5725c751b772b4edc70 (diff) | |
| download | gem5-ba33db8fd66fe0814a59d520df54f0bb3788ce1d.tar.xz | |
ARM: Decode the CPS instruction.
Diffstat (limited to 'src/arch/arm/isa/formats/uncond.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/uncond.isa | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/arch/arm/isa/formats/uncond.isa b/src/arch/arm/isa/formats/uncond.isa index 45cdbd058..0aa57a261 100644 --- a/src/arch/arm/isa/formats/uncond.isa +++ b/src/arch/arm/isa/formats/uncond.isa @@ -46,7 +46,12 @@ def format ArmUnconditional() {{ if (bits((uint32_t)rn, 0) == 1 && op2 == 0) { return new Setend(machInst, bits(machInst, 9)); } else if (bits((uint32_t)rn, 0) == 0 && bits(op2, 1) == 0) { - return new WarnUnimplemented("cps", machInst); + const bool enable = bits(machInst, 19, 18) == 0x2; + const uint32_t mods = bits(machInst, 4, 0) | + (bits(machInst, 8, 6) << 5) | + (bits(machInst, 17) << 8) | + ((enable ? 1 : 0) << 9); + return new Cps(machInst, mods); } } else if (bits(op1, 6, 5) == 0x1) { return new WarnUnimplemented( |