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author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:19 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:19 -0700 |
commit | 826a3582ea92ea1fe2597a6cfb6853626d3c808e (patch) | |
tree | 1dcda813bbab13f17501f4bdafc2bc105365a1ad /src/arch/arm/isa/formats/util.isa | |
parent | 17f0943398fb403c189dc3f6f4d0d834d56f061c (diff) | |
download | gem5-826a3582ea92ea1fe2597a6cfb6853626d3c808e.tar.xz |
ARM: Don't always update CPSR.
Diffstat (limited to 'src/arch/arm/isa/formats/util.isa')
-rw-r--r-- | src/arch/arm/isa/formats/util.isa | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/arch/arm/isa/formats/util.isa b/src/arch/arm/isa/formats/util.isa index 5caab642c..ac2e077ba 100644 --- a/src/arch/arm/isa/formats/util.isa +++ b/src/arch/arm/isa/formats/util.isa @@ -35,7 +35,6 @@ def ArmGenericCodeSubs(code): # Substitute in the shifted portion of operations new_code = re.sub(r'Rm_Imm', 'shift_rm_imm(Rm, shift_size, shift, Cpsr<29:>)', code) new_code = re.sub(r'Rm_Rs', 'shift_rm_rs(Rm, Rs, shift, Cpsr<29:>)', new_code) - new_code = re.sub(r'^', 'Cpsr = Cpsr;', new_code) return new_code def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, |