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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-11-08 02:08:40 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-11-08 02:08:40 -0800 |
| commit | 48525f581c6233b8f7a8a872c5774d4e245f431c (patch) | |
| tree | d6bfb77abb6e70684f04d21b47731ed7a02bcf94 /src/arch/arm/isa/formats/util.isa | |
| parent | d188821d3700ee42e01fc43c9ef17568991fb3ff (diff) | |
| download | gem5-48525f581c6233b8f7a8a872c5774d4e245f431c.tar.xz | |
ARM: Split the condition codes out of the CPSR.
This allows those bits to be renamed while allowing the other fields to
control the behavior of the processor.
Diffstat (limited to 'src/arch/arm/isa/formats/util.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/util.isa | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/arch/arm/isa/formats/util.isa b/src/arch/arm/isa/formats/util.isa index b5efec568..d42ffb147 100644 --- a/src/arch/arm/isa/formats/util.isa +++ b/src/arch/arm/isa/formats/util.isa @@ -33,8 +33,10 @@ let {{ # Generic substitutions for Arm instructions def ArmGenericCodeSubs(code): # Substitute in the shifted portion of operations - new_code = re.sub(r'Rm_Imm', 'shift_rm_imm(Rm, shift_size, shift, Cpsr<29:>)', code) - new_code = re.sub(r'Rm_Rs', 'shift_rm_rs(Rm, Rs, shift, Cpsr<29:>)', new_code) + new_code = re.sub(r'Rm_Imm', + 'shift_rm_imm(Rm, shift_size, shift, CondCodes<29:>)', code) + new_code = re.sub(r'Rm_Rs', + 'shift_rm_rs(Rm, Rs, shift, CondCodes<29:>)', new_code) return new_code def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, |