diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:02 -0500 |
---|---|---|
committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:02 -0500 |
commit | 64d6b6ebfd4da3c4facb9f584a362949eed6a1ed (patch) | |
tree | 8948b3b7fad0cc8aa5f545e037da1459b689d59c /src/arch/arm/isa/formats | |
parent | 51bde086d578e09e1058b17c40fae99404a325dc (diff) | |
download | gem5-64d6b6ebfd4da3c4facb9f584a362949eed6a1ed.tar.xz |
ARM: Hook up 16 bit thumb load/store multiple.
Diffstat (limited to 'src/arch/arm/isa/formats')
-rw-r--r-- | src/arch/arm/isa/formats/macromem.isa | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/macromem.isa b/src/arch/arm/isa/formats/macromem.isa index 95b7ccd6a..98505be84 100644 --- a/src/arch/arm/isa/formats/macromem.isa +++ b/src/arch/arm/isa/formats/macromem.isa @@ -43,3 +43,16 @@ def format ArmMacroMem() {{ PSRUSER, WRITEBACK, LOADOP, machInst.regList); ''' }}; + +def format Thumb16MacroMem() {{ + decode_block = ''' + { + const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); + const bool load = (bits(machInst, 11) == 1); + const uint32_t regList = bits(machInst, 7, 0); + const bool writeback = (!load || bits(regList, rn) == 0); + return new LdmStm(machInst, rn, true, true, false, + writeback, load, regList); + } + ''' +}}; |