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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-01 22:15:39 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-01 22:15:39 -0700 |
| commit | ce9cb1ecb5844aa589ebfef348d8731c3228acad (patch) | |
| tree | 20c481d82ba1bd0147ce049cf9048774ee6d2bb1 /src/arch/arm/isa/formats | |
| parent | 776a06fd394bc9a55b25524c47d54420880ebd11 (diff) | |
| download | gem5-ce9cb1ecb5844aa589ebfef348d8731c3228acad.tar.xz | |
ARM: Centralize the declaration of resTemp.
Diffstat (limited to 'src/arch/arm/isa/formats')
| -rw-r--r-- | src/arch/arm/isa/formats/pred.isa | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa index 51d383d6a..ef53843ae 100644 --- a/src/arch/arm/isa/formats/pred.isa +++ b/src/arch/arm/isa/formats/pred.isa @@ -41,6 +41,8 @@ def template PredOpExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; + uint64_t resTemp = 0; + resTemp = resTemp; %(op_decl)s; %(op_rd)s; @@ -100,7 +102,6 @@ let {{ }}; def format DataOp(code, icValue, ivValue) {{ - code += "resTemp = resTemp;" regCode = re.sub(r'op2', 'shift_rm_rs(Rm, Rs, \ shift, Cpsr<29:0>)', code) immCode = re.sub(r'op2', 'shift_rm_imm(Rm, shift_size, \ |