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authorMatt Horsnell <Matt.Horsnell@arm.com>2012-03-01 17:26:31 -0600
committerMatt Horsnell <Matt.Horsnell@arm.com>2012-03-01 17:26:31 -0600
commit08187e3916fa615444ed61d739ac91e284735a66 (patch)
tree27e62a6b77e396b2e848ae5d1a2b368e81add490 /src/arch/arm/isa/formats
parentd907d0ec723538c7969bf8f2f2d6f29439b02985 (diff)
downloadgem5-08187e3916fa615444ed61d739ac91e284735a66.tar.xz
ARM: Add limited CP14 support.
New kernels attempt to read CP14 what debug architecture is available. These changes add the debug registers and return that none is currently available.
Diffstat (limited to 'src/arch/arm/isa/formats')
-rw-r--r--src/arch/arm/isa/formats/misc.isa45
-rw-r--r--src/arch/arm/isa/formats/uncond.isa4
2 files changed, 47 insertions, 2 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 54482864a..3865cffe2 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2010 ARM Limited
+// Copyright (c) 2010-2012 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -85,6 +85,49 @@ let {{
'''
decoder_output = '''
StaticInstPtr
+ decodeMcrMrc14(ExtMachInst machInst)
+ {
+ const uint32_t opc1 = bits(machInst, 23, 21);
+ const uint32_t crn = bits(machInst, 19, 16);
+ const uint32_t opc2 = bits(machInst, 7, 5);
+ const uint32_t crm = bits(machInst, 3, 0);
+ const MiscRegIndex miscReg = decodeCP14Reg(crn, opc1, crm, opc2);
+ const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+
+ const bool isRead = bits(machInst, 20);
+
+ switch (miscReg) {
+ case MISCREG_NOP:
+ return new NopInst(machInst);
+ case NUM_MISCREGS:
+ return new FailUnimplemented(
+ csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
+ crn, opc1, crm, opc2, isRead ? "read" : "write").c_str(),
+ machInst);
+ default:
+ if (isRead) {
+ return new Mrc14(machInst, rt, (IntRegIndex)miscReg);
+ } else {
+ return new Mcr14(machInst, (IntRegIndex)miscReg, rt);
+ }
+ }
+ }
+ '''
+}};
+
+def format McrMrc14() {{
+ decode_block = '''
+ return decodeMcrMrc14(machInst);
+ '''
+}};
+
+let {{
+ header_output = '''
+ StaticInstPtr
+ decodeMcrMrc15(ExtMachInst machInst);
+ '''
+ decoder_output = '''
+ StaticInstPtr
decodeMcrMrc15(ExtMachInst machInst)
{
const uint32_t opc1 = bits(machInst, 23, 21);
diff --git a/src/arch/arm/isa/formats/uncond.isa b/src/arch/arm/isa/formats/uncond.isa
index 0ef113607..4a18a55bb 100644
--- a/src/arch/arm/isa/formats/uncond.isa
+++ b/src/arch/arm/isa/formats/uncond.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2010 ARM Limited
+// Copyright (c) 2010-2012 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -269,6 +269,8 @@ def format ArmUnconditional() {{
if (bits(op1, 4) == 0) {
if (CPNUM == 0xa || CPNUM == 0xb) {
return decodeShortFpTransfer(machInst);
+ } else if (CPNUM == 0xe) {
+ return decodeMcrMrc14(machInst);
} else if (CPNUM == 0xf) {
return decodeMcrMrc15(machInst);
}