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author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2017-11-10 15:35:26 +0000 |
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committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2017-11-21 14:25:56 +0000 |
commit | 2a2c66c16c659af4c3588b6c1646d55c66ad53fe (patch) | |
tree | 633dd84e28b040febbe2fd2efc7cd0a62dc7f60d /src/arch/arm/isa/formats | |
parent | d3ec34201c14d551e864372a89ccddb1c255e77a (diff) | |
download | gem5-2a2c66c16c659af4c3588b6c1646d55c66ad53fe.tar.xz |
arch-arm: Fix MSR/MRS disassemble
This patch is fixing the Aarch64 MSR/MRS disassemble, which was
previously printing unexisting integer registers as source/destination
operands rather than the system register name
Change-Id: Iac9d5f2f2fea85abd9a398320ef7aa4844d43c0e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5861
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/formats')
-rw-r--r-- | src/arch/arm/isa/formats/aarch64.isa | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index 2c33e2441..d640caf09 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -369,12 +369,13 @@ namespace Aarch64 return new Dczva(machInst, rt, (IntRegIndex) miscReg, iss); if (read) { - StaticInstPtr si = new Mrs64(machInst, rt, (IntRegIndex) miscReg, iss); + StaticInstPtr si = new Mrs64(machInst, rt, miscReg, iss); if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE]) si->setFlag(StaticInst::IsUnverifiable); return si; - } else - return new Msr64(machInst, (IntRegIndex) miscReg, rt, iss); + } else { + return new Msr64(machInst, miscReg, rt, iss); + } } else if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { std::string full_mnem = csprintf("%s %s", read ? "mrs" : "msr", miscRegName[miscReg]); |