diff options
author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2017-10-13 10:03:14 +0100 |
---|---|---|
committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-11-15 14:11:44 +0000 |
commit | ef0490081fa7ebcda2e1c7adccb05b3a14014cf1 (patch) | |
tree | 8073449559fecaf9bc1fb8f280a50a30a9313863 /src/arch/arm/isa/formats | |
parent | f0f04ddd70aa3260f5282227de264653ac36fabe (diff) | |
download | gem5-ef0490081fa7ebcda2e1c7adccb05b3a14014cf1.tar.xz |
arm: Add support for armv8 CRC32 instructions
This patch introduces the ARM A32/T32/A64 CRC Instructions, which are
mandatory since ARMv8.1. The UNPREDICTABLE behaviours are implemented as
follows:
1) CRC32(C)X (64 bit) instructions are decoded as Undefined in Aarch32
2) The instructions support predication in Aarch32
3) Using R15(PC) as source/dest operand is permitted in Aarch32
Change-Id: Iaf29b05874e1370c7615da79a07f111ded17b6cc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5521
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/formats')
-rw-r--r-- | src/arch/arm/isa/formats/aarch64.isa | 16 | ||||
-rw-r--r-- | src/arch/arm/isa/formats/data.isa | 25 | ||||
-rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 31 |
3 files changed, 70 insertions, 2 deletions
diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index 38e5b15a0..2c33e2441 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -1202,6 +1202,22 @@ namespace Aarch64 return new Asrv64(machInst, rdzr, rn, rm); case 0xb: return new Rorv64(machInst, rdzr, rn, rm); + case 0x10: + return new Crc32b64(machInst, rdzr, rn, rm); + case 0x11: + return new Crc32h64(machInst, rdzr, rn, rm); + case 0x12: + return new Crc32w64(machInst, rdzr, rn, rm); + case 0x13: + return new Crc32x64(machInst, rdzr, rn, rm); + case 0x14: + return new Crc32cb64(machInst, rdzr, rn, rm); + case 0x15: + return new Crc32ch64(machInst, rdzr, rn, rm); + case 0x16: + return new Crc32cw64(machInst, rdzr, rn, rm); + case 0x17: + return new Crc32cx64(machInst, rdzr, rn, rm); default: return new Unknown64(machInst); } diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa index 3ee178f0e..909a52593 100644 --- a/src/arch/arm/isa/formats/data.isa +++ b/src/arch/arm/isa/formats/data.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2010 ARM Limited +// Copyright (c) 2010,2017 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -788,7 +788,7 @@ def format Thumb32DataProcReg() {{ } } } else if (bits(op1, 3, 2) == 0x2 && bits(op2, 3, 2) == 0x2) { - const uint32_t op1 = bits(machInst, 21, 20); + const uint32_t op1 = bits(machInst, 22, 20); const uint32_t op2 = bits(machInst, 5, 4); const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); @@ -832,6 +832,27 @@ def format Thumb32DataProcReg() {{ if (op2 == 0) { return new Clz(machInst, rd, rm); } + break; + case 0x4: + switch (op2) { + case 0x0: + return new Crc32b(machInst, rd, rn, rm); + case 0x1: + return new Crc32h(machInst, rd, rn, rm); + case 0x2: + return new Crc32w(machInst, rd, rn, rm); + } + break; + case 0x5: + switch (op2) { + case 0x0: + return new Crc32cb(machInst, rd, rn, rm); + case 0x1: + return new Crc32ch(machInst, rd, rn, rm); + case 0x2: + return new Crc32cw(machInst, rd, rn, rm); + } + break; } } return new Unknown(machInst); diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 43a7cc975..26681e40f 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -38,6 +38,37 @@ // Authors: Gabe Black // Giacomo Gabrielli +def format Crc32() {{ + decode_block = ''' + { + const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); + const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); + const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); + + uint8_t c_poly = bits(machInst, 9); + uint8_t sz = bits(machInst, 22, 21); + uint8_t crc_select = (c_poly << 2) | sz; + + switch(crc_select) { + case 0x0: + return new Crc32b(machInst, rd, rn, rm); + case 0x1: + return new Crc32h(machInst, rd, rn, rm); + case 0x2: + return new Crc32w(machInst, rd, rn, rm); + case 0x4: + return new Crc32cb(machInst, rd, rn, rm); + case 0x5: + return new Crc32ch(machInst, rd, rn, rm); + case 0x6: + return new Crc32cw(machInst, rd, rn, rm); + default: + return new Unknown(machInst); + } + } + ''' +}}; + def format ArmERet() {{ decode_block = "return new Eret(machInst);" }}; |