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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:07 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:07 -0500 |
| commit | 00320a53ab67e5f7b7a22b67f6b14ade31348c50 (patch) | |
| tree | 8236db18e50130c025232de5cbbce21dda3871a3 /src/arch/arm/isa/formats | |
| parent | 5cc1bb684226d9a67cd6868720a6ca2c267592d6 (diff) | |
| download | gem5-00320a53ab67e5f7b7a22b67f6b14ade31348c50.tar.xz | |
ARM: Decode the rbit instruction.
Diffstat (limited to 'src/arch/arm/isa/formats')
| -rw-r--r-- | src/arch/arm/isa/formats/data.isa | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa index 51cb4fd03..9dca0e8a3 100644 --- a/src/arch/arm/isa/formats/data.isa +++ b/src/arch/arm/isa/formats/data.isa @@ -283,26 +283,26 @@ def format ArmPackUnpackSatReverse() {{ } break; case 0x7: - if (op2 == 0x1) { - return new WarnUnimplemented("rbit", machInst); - } else if (op2 == 0x3) { + { const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); - const uint32_t rotation = - (uint32_t)bits(machInst, 11, 10) << 3; - if (a == 0xf) { - return new Uxth(machInst, rd, rotation, rm); - } else { - return new Uxtah(machInst, rd, rn, rm, rotation); + if (op2 == 0x1) { + return new Rbit(machInst, rd, rm); + } else if (op2 == 0x3) { + const uint32_t rotation = + (uint32_t)bits(machInst, 11, 10) << 3; + if (a == 0xf) { + return new Uxth(machInst, rd, rotation, rm); + } else { + return new Uxtah(machInst, rd, rn, rm, rotation); + } + } else if (op2 == 0x5) { + return new Revsh(machInst, rd, rm); } - } else if (op2 == 0x5) { - IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); - IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); - return new Revsh(machInst, rd, rm); } break; } @@ -791,7 +791,7 @@ def format Thumb32DataProcReg() {{ case 0x1: return new Rev16(machInst, rd, rn); case 0x2: - return new WarnUnimplemented("rbit", machInst); + return new Rbit(machInst, rd, rm); case 0x3: return new Revsh(machInst, rd, rn); } |