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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-01 22:16:05 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-01 22:16:05 -0700 |
| commit | 22a1ac22f4015bb3fd6450c2643d647d5df97db8 (patch) | |
| tree | ee231e532e24f8045dbbd9924500a867c5609776 /src/arch/arm/isa/formats | |
| parent | ce9cb1ecb5844aa589ebfef348d8731c3228acad (diff) | |
| download | gem5-22a1ac22f4015bb3fd6450c2643d647d5df97db8.tar.xz | |
ARM: Get rid of the val2 variable.
Diffstat (limited to 'src/arch/arm/isa/formats')
| -rw-r--r-- | src/arch/arm/isa/formats/pred.isa | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa index ef53843ae..dc115f588 100644 --- a/src/arch/arm/isa/formats/pred.isa +++ b/src/arch/arm/isa/formats/pred.isa @@ -102,10 +102,12 @@ let {{ }}; def format DataOp(code, icValue, ivValue) {{ - regCode = re.sub(r'op2', 'shift_rm_rs(Rm, Rs, \ - shift, Cpsr<29:0>)', code) - immCode = re.sub(r'op2', 'shift_rm_imm(Rm, shift_size, \ - shift, Cpsr<29:0>)', code) + regCode = '''uint32_t op2 = shift_rm_rs(Rm, Rs, + shift, Cpsr<29:0>); + op2 = op2;''' + code + immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size, + shift, Cpsr<29:0>); + op2 = op2;''' + code regIop = InstObjParams(name, Name, 'PredIntOp', {"code": regCode, "predicate_test": predicateTest}) |