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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:02 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:02 -0500 |
| commit | 05866c82f9eb80db05fb423addcc8563efe1b744 (patch) | |
| tree | dc5d03a1f3021a979705dc66de9598d721812bb4 /src/arch/arm/isa/formats | |
| parent | 401165c778108ab22aeeee55c4f4451ca93bcffb (diff) | |
| download | gem5-05866c82f9eb80db05fb423addcc8563efe1b744.tar.xz | |
ARM: Construct the predicate test register for more instruction programatically.
If one of the condition codes isn't being used in the execution we should only
read it if the instruction might be dependent on it. With the preeceding changes
there are several more cases where we should dynamically pick instead of assuming
as we did before.
Diffstat (limited to 'src/arch/arm/isa/formats')
| -rw-r--r-- | src/arch/arm/isa/formats/pred.isa | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa index bd6ccddd1..b9745e8ba 100644 --- a/src/arch/arm/isa/formats/pred.isa +++ b/src/arch/arm/isa/formats/pred.isa @@ -48,10 +48,10 @@ let {{ CpsrQ = (Rd < resTemp) ? 1 << 27 : 0; } else { uint16_t _ic, _iv, _iz, _in; - _in = (resTemp >> %(negBit)d) & 1; + _in = (resTemp >> %(negBit)d); _iz = (resTemp == 0); - _iv = %(ivValue)s & 1; - _ic = %(icValue)s & 1; + _iv = %(ivValue)s; + _ic = %(icValue)s; CondCodesNZ = (_in << 1) | (_iz); CondCodesC = _ic; @@ -138,23 +138,23 @@ let {{ def format DataOp(code, flagtype = logic) {{ (regCcCode, immCcCode) = getCcCode(flagtype) regCode = '''uint32_t op2 = shift_rm_rs(Rm, Rs<7:0>, - shift, CondCodesC); + shift, 0); op2 = op2;''' + code immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size, - shift, CondCodesC); + shift, OptShiftRmCondCodesC); op2 = op2;''' + code regIop = InstObjParams(name, Name, 'PredIntOp', {"code": regCode, - "predicate_test": predicateTest}) + "predicate_test": pickPredicate(regCode)}) immIop = InstObjParams(name, Name + "Imm", 'PredIntOp', {"code": immCode, - "predicate_test": predicateTest}) + "predicate_test": pickPredicate(imm)}) regCcIop = InstObjParams(name, Name + "Cc", 'PredIntOp', - {"code": regCode + regCcCode, - "predicate_test": condPredicateTest}) + {"code": regCode + regCcCode, + "predicate_test": pickPredicate(regCode + regCcCode)}) immCcIop = InstObjParams(name, Name + "ImmCc", 'PredIntOp', - {"code": immCode + immCcCode, - "predicate_test": condPredicateTest}) + {"code": immCode + immCcCode, + "predicate_test": pickPredicate(immCode + immCcCode)}) header_output = BasicDeclare.subst(regIop) + \ BasicDeclare.subst(immIop) + \ BasicDeclare.subst(regCcIop) + \ @@ -174,10 +174,10 @@ def format DataImmOp(code, flagtype = logic) {{ code += "resTemp = resTemp;" iop = InstObjParams(name, Name, 'PredImmOp', {"code": code, - "predicate_test": predicateTest}) + "predicate_test": pickPredicate(code)}) ccIop = InstObjParams(name, Name + "Cc", 'PredImmOp', - {"code": code + getImmCcCode(flagtype), - "predicate_test": condPredicateTest}) + {"code": code + getImmCcCode(flagtype), + "predicate_test": pickPredicate(code + getImmCcCode(flagtype))}) header_output = BasicDeclare.subst(iop) + \ BasicDeclare.subst(ccIop) decoder_output = BasicConstructor.subst(iop) + \ @@ -190,7 +190,7 @@ def format DataImmOp(code, flagtype = logic) {{ def format PredOp(code, *opt_flags) {{ iop = InstObjParams(name, Name, 'PredOp', {"code": code, - "predicate_test": predicateTest}, + "predicate_test": pickPredicate(code)}, opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) @@ -201,7 +201,7 @@ def format PredOp(code, *opt_flags) {{ def format PredImmOp(code, *opt_flags) {{ iop = InstObjParams(name, Name, 'PredImmOp', {"code": code, - "predicate_test": predicateTest}, + "predicate_test": pickPredicate(code)}, opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) |