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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:17 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:17 -0500 |
| commit | 0e556e9dfbd9a3b3f06a023d4edf3b3678fd0a40 (patch) | |
| tree | f65f9bff359637704083eff566945d66782abec7 /src/arch/arm/isa/formats | |
| parent | 3dc6a8070ec8cbe9d5764aed9ff4437826183be8 (diff) | |
| download | gem5-0e556e9dfbd9a3b3f06a023d4edf3b3678fd0a40.tar.xz | |
ARM: Treat LDRD in ARM with an odd index as an undefined instruction.
Diffstat (limited to 'src/arch/arm/isa/formats')
| -rw-r--r-- | src/arch/arm/isa/formats/mem.isa | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa index aa8bbf55e..59a6f126a 100644 --- a/src/arch/arm/isa/formats/mem.isa +++ b/src/arch/arm/isa/formats/mem.isa @@ -122,8 +122,10 @@ def format AddrMode3() {{ case 0x2: if (op1 & 0x1) { %(ldrsb)s - } else { + } else if ((RT %% 2) == 0) { %(ldrd)s + } else { + return new Unknown(machInst); } case 0x3: if (op1 & 0x1) { |