summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa/formats
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:09 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:09 -0500
commit9d4a1bf2ba936499277b96054fbc83c478c0c6be (patch)
treed4ced7dbf19e8c0e044bec654f3ea1c82cd809cf /src/arch/arm/isa/formats
parent28023f6f3d752fe600e4f610549ae27541b2ebce (diff)
downloadgem5-9d4a1bf2ba936499277b96054fbc83c478c0c6be.tar.xz
ARM: Explicitly keep track of the second destination for double loads/stores.
Diffstat (limited to 'src/arch/arm/isa/formats')
-rw-r--r--src/arch/arm/isa/formats/mem.isa12
1 files changed, 8 insertions, 4 deletions
diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa
index 311ae5b66..1c69a5e00 100644
--- a/src/arch/arm/isa/formats/mem.isa
+++ b/src/arch/arm/isa/formats/mem.isa
@@ -150,6 +150,10 @@ def format AddrMode3() {{
addStr = "true"
else:
addStr = "false"
+ if d:
+ dests = "RT & ~1, RT | 1"
+ else:
+ dests = "RT"
if i:
if load:
if d:
@@ -165,8 +169,8 @@ def format AddrMode3() {{
className = storeImmClassName(post, add, writeback, \
size=size, sign=sign, \
user=user)
- decode += ("%s(machInst, RT, RN, %s, imm);\n" % \
- (className, addStr))
+ decode += ("%s(machInst, %s, RN, %s, imm);\n" % \
+ (className, dests, addStr))
else:
if load:
if d:
@@ -182,8 +186,8 @@ def format AddrMode3() {{
className = storeRegClassName(post, add, writeback, \
size=size, sign=sign, \
user=user)
- decode += ("%s(machInst, RT, RN, %s, 0, LSL, RM);\n" % \
- (className, addStr))
+ decode += ("%s(machInst, %s, RN, %s, 0, LSL, RM);\n" % \
+ (className, dests, addStr))
return decode
def decodePuiw(load, d, size=4, sign=False):