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authorAli Saidi <Ali.Saidi@ARM.com>2010-06-02 12:58:16 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2010-06-02 12:58:16 -0500
commitcb9936cfdefdebf2c0b950f93a62d504d356524d (patch)
tree3280784b875ccd23475c3f08edc774b50ef1c97d /src/arch/arm/isa/formats
parentf246be4cbc27b4173f6917b430a31b9a39cdb380 (diff)
downloadgem5-cb9936cfdefdebf2c0b950f93a62d504d356524d.tar.xz
ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.
Diffstat (limited to 'src/arch/arm/isa/formats')
-rw-r--r--src/arch/arm/isa/formats/misc.isa34
1 files changed, 6 insertions, 28 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 1c00a3d6b..be0e63900 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -138,47 +138,25 @@ let {{
return new WarnUnimplemented(
isRead ? "mrc bpiall" : "mcr bpiall", machInst);
case MISCREG_TLBIALLIS:
- return new WarnUnimplemented(
- isRead ? "mrc tlbiallis" : "mcr tlbiallis", machInst);
case MISCREG_TLBIMVAIS:
- return new WarnUnimplemented(
- isRead ? "mrc tlbimvais" : "mcr tlbimvais", machInst);
case MISCREG_TLBIASIDIS:
- return new WarnUnimplemented(
- isRead ? "mrc tlbiasidis" : "mcr tlbiasidis", machInst);
case MISCREG_TLBIMVAAIS:
- return new WarnUnimplemented(
- isRead ? "mrc tlbimvaais" : "mcr tlbimvaais", machInst);
case MISCREG_ITLBIALL:
- return new WarnUnimplemented(
- isRead ? "mrc itlbiall" : "mcr itlbiall", machInst);
case MISCREG_ITLBIMVA:
- return new WarnUnimplemented(
- isRead ? "mrc itlbimva" : "mcr itlbimva", machInst);
case MISCREG_ITLBIASID:
- return new WarnUnimplemented(
- isRead ? "mrc itlbiasid" : "mcr itlbiasid", machInst);
case MISCREG_DTLBIALL:
- return new WarnUnimplemented(
- isRead ? "mrc dtlbiall" : "mcr dtlbiall", machInst);
case MISCREG_DTLBIMVA:
- return new WarnUnimplemented(
- isRead ? "mrc dtlbimva" : "mcr dtlbimva", machInst);
case MISCREG_DTLBIASID:
- return new WarnUnimplemented(
- isRead ? "mrc dtlbiasid" : "mcr dtlbiasid", machInst);
case MISCREG_TLBIALL:
- return new WarnUnimplemented(
- isRead ? "mrc tlbiall" : "mcr tlbiall", machInst);
case MISCREG_TLBIMVA:
- return new WarnUnimplemented(
- isRead ? "mrc tlbimva" : "mcr tlbimva", machInst);
case MISCREG_TLBIASID:
- return new WarnUnimplemented(
- isRead ? "mrc tlbiasid" : "mcr tlbiasid", machInst);
case MISCREG_TLBIMVAA:
- return new WarnUnimplemented(
- isRead ? "mrc tlbimvaa" : "mcr tlbimvaa", machInst);
+ if (isRead) {
+ return new Unknown(machInst);
+ } else {
+ return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
+ }
+
default:
if (isRead) {
return new Mrc15(machInst, rt, (IntRegIndex)miscReg);