arch-arm: AArch64 Crypto AES

This patch implements the AArch64 AES instructions
from the Crypto extension.

Change-Id: I9143041ec7e1c6a50dcad3f72d7d1b55d6f2d402
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13250
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

2 files changed, 28 insertions, 0 deletions

diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa
index 241f9637f..aa38fd426 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -1467,6 +1467,8 @@ namespace Aarch64
                 return decodeNeon3Diff(machInst);
             } else if (bits(machInst, 20, 17) == 0x0) {
                 return decodeNeon2RegMisc(machInst);
+            } else if (bits(machInst, 20, 17) == 0x4) {
+                return decodeCryptoAES(machInst);
             } else if (bits(machInst, 20, 17) == 0x8) {
                 return decodeNeonAcrossLanes(machInst);
             } else {
diff --git a/src/arch/arm/isa/formats/crypto64.isa b/src/arch/arm/isa/formats/crypto64.isa
index 8975c2d93..d155b0421 100644
--- a/src/arch/arm/isa/formats/crypto64.isa
+++ b/src/arch/arm/isa/formats/crypto64.isa
@@ -40,6 +40,9 @@
 let {{
     header_output = '''
     StaticInstPtr
+    decodeCryptoAES(ExtMachInst machInst);
+
+    StaticInstPtr
     decodeCryptoThreeRegSHA(ExtMachInst machInst);
 
     StaticInstPtr
@@ -49,6 +52,29 @@ let {{
     decoder_output = '''
 
     StaticInstPtr
+    decodeCryptoAES(ExtMachInst machInst)
+    {
+        const auto opcode = bits(machInst, 16, 12);
+        const auto size = bits(machInst, 23, 22);
+
+        IntRegIndex rd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
+        IntRegIndex rn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+
+        if (size) {
+            // UNALLOCATED
+            return new Unknown64(machInst);
+        } else {
+            switch (opcode) {
+              case 0x4: return new AESE64(machInst, rd, rd, rn);
+              case 0x5: return new AESD64(machInst, rd, rd, rn);
+              case 0x6: return new AESMC64(machInst, rd, rn);
+              case 0x7: return new AESIMC64(machInst, rd, rn);
+              default: return new Unknown64(machInst);
+            }
+        }
+    }
+
+    StaticInstPtr
     decodeCryptoTwoRegSHA(ExtMachInst machInst)
     {
         const auto opcode = bits(machInst, 16, 12);