arch-arm: Add first-/non-faulting load instructions

First-/non-faulting loads are part of Arm SVE.

Change-Id: I93dfd6d1d74791653927e99098ddb651150a8ef7
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19177
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

1 files changed, 35 insertions, 40 deletions

diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa b/src/arch/arm/isa/formats/sve_2nd_level.isa
index d4e75285b..69d80e294 100644
--- a/src/arch/arm/isa/formats/sve_2nd_level.isa
+++ b/src/arch/arm/isa/formats/sve_2nd_level.isa
@@ -2921,9 +2921,6 @@ namespace Aarch64
                     uint8_t dtype = (bits(machInst, 24, 23) << 1) |
                                     bits(machInst, 14);
                     uint8_t ff = bits(machInst, 13);
-                    if (ff) {
-                        return new Unknown64(machInst);
-                    }
                     return decodeSveGatherLoadVIInsts(
                         dtype, machInst, zt, pg, zn, imm, true, ff);
                 } else {
@@ -2952,9 +2949,6 @@ namespace Aarch64
                                 bits(machInst, 14);
                 uint8_t xs = bits(machInst, 22);
                 uint8_t ff = bits(machInst, 13);
-                if (ff) {
-                    return new Unknown64(machInst);
-                }
                 return decodeSveGatherLoadSVInsts(
                         dtype, machInst, zt, pg, rn, zm,
                         true, true, xs, false, ff);
@@ -2980,19 +2974,20 @@ namespace Aarch64
                              bits(machInst, 12, 10);
                     uint8_t xs = bits(machInst, 22);
                     uint8_t ff = bits(machInst, 13);
-                    if (ff) {
-                        return new Unknown64(machInst);
-                    }
                     if (bits(machInst, 14)) {
-                        return new SveIndexedMemSV<uint32_t, uint16_t,
-                                                   SveGatherLoadSVMicroop>(
-                            "ld1", machInst, MemReadOp, zt, pg, rn, zm,
-                            true, xs, true);
+                        return
+                           new SveIndexedMemSV<uint32_t, uint16_t,
+                                               SveGatherLoadSVMicroop,
+                                               SveFirstFaultWritebackMicroop>(
+                            ff ? "ldff1" : "ld1", machInst, MemReadOp, zt, pg,
+                            rn, zm, true, xs, true, ff);
                     } else {
-                        return new SveIndexedMemSV<int32_t, int16_t,
-                                                   SveGatherLoadSVMicroop>(
-                            "ld1", machInst, MemReadOp, zt, pg, rn, zm,
-                            true, xs, true);
+                        return
+                           new SveIndexedMemSV<int32_t, int16_t,
+                                               SveGatherLoadSVMicroop,
+                                               SveFirstFaultWritebackMicroop>(
+                            ff ? "ldff1" : "ld1", machInst, MemReadOp, zt, pg,
+                            rn, zm, true, xs, true, ff);
                     }
                 }
                 break;
@@ -3010,13 +3005,11 @@ namespace Aarch64
                              bits(machInst, 12, 10);
                     uint8_t xs = bits(machInst, 22);
                     uint8_t ff = bits(machInst, 13);
-                    if (ff) {
-                        return new Unknown64(machInst);
-                    }
                     return new SveIndexedMemSV<uint32_t, uint32_t,
-                                               SveGatherLoadSVMicroop>(
-                        "ld1", machInst, MemReadOp, zt, pg, rn, zm,
-                        true, xs, true);
+                                               SveGatherLoadSVMicroop,
+                                               SveFirstFaultWritebackMicroop>(
+                        ff ? "ldff1" : "ld1", machInst, MemReadOp, zt, pg, rn,
+                        zm, true, xs, true, ff);
                 }
                 break;
               case 0x3:
@@ -3083,7 +3076,18 @@ namespace Aarch64
     StaticInstPtr
     decodeSveContigFFLoadSS(ExtMachInst machInst)
     {
-        return new Unknown64(machInst);
+        IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
+        IntRegIndex rn = makeSP((IntRegIndex) (uint8_t) bits(machInst, 9, 5));
+        IntRegIndex rm = makeSP(
+            (IntRegIndex) (uint8_t) bits(machInst, 20, 16));
+        IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+
+        if (rm == 0x1f) {
+            return new Unknown64(machInst);
+        }
+
+        return decodeSveContigLoadSSInsts<SveContigFFLoadSS>(
+            bits(machInst, 24, 21), machInst, zt, pg, rn, rm, true);
     }  // decodeSveContigFFLoadSS
 
     StaticInstPtr
@@ -3101,7 +3105,13 @@ namespace Aarch64
     StaticInstPtr
     decodeSveContigNFLoadSI(ExtMachInst machInst)
     {
-        return new Unknown64(machInst);
+        IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
+        IntRegIndex rn = makeSP((IntRegIndex) (uint8_t) bits(machInst, 9, 5));
+        uint64_t imm = sext<4>(bits(machInst, 19, 16));
+        IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+
+        return decodeSveContigLoadSIInsts<SveContigNFLoadSI>(
+            bits(machInst, 24, 21), machInst, zt, pg, rn, imm, true);
     }  // decodeSveContigNFLoadSI
 
     StaticInstPtr
@@ -3186,9 +3196,6 @@ namespace Aarch64
                                 bits(machInst, 14);
                 uint8_t xs = bits(machInst, 22);
                 uint8_t ff = bits(machInst, 13);
-                if (ff) {
-                    return new Unknown64(machInst);
-                }
                 return decodeSveGatherLoadSVInsts(
                         dtype, machInst, zt, pg, rn, zm,
                         false, true, xs, false, ff);
@@ -3205,9 +3212,6 @@ namespace Aarch64
                 uint8_t dtype = (bits(machInst, 24, 23) << 1) |
                                 bits(machInst, 14);
                 uint8_t ff = bits(machInst, 13);
-                if (ff) {
-                    return new Unknown64(machInst);
-                }
                 return decodeSveGatherLoadSVInsts(
                         dtype, machInst, zt, pg, rn, zm,
                         false, false, false, false, ff);
@@ -3232,9 +3236,6 @@ namespace Aarch64
                                 bits(machInst, 14);
                 uint8_t xs = bits(machInst, 22);
                 uint8_t ff = bits(machInst, 13);
-                if (ff) {
-                    return new Unknown64(machInst);
-                }
                 return decodeSveGatherLoadSVInsts(
                         dtype, machInst, zt, pg, rn, zm,
                         false, true, xs, true, ff);
@@ -3255,9 +3256,6 @@ namespace Aarch64
                 uint8_t dtype = (bits(machInst, 24, 23) << 1) |
                                 bits(machInst, 14);
                 uint8_t ff = bits(machInst, 13);
-                if (ff) {
-                    return new Unknown64(machInst);
-                }
                 return decodeSveGatherLoadVIInsts(
                     dtype, machInst, zt, pg, zn, imm, false, ff);
             } else {
@@ -3275,9 +3273,6 @@ namespace Aarch64
                     uint8_t dtype = (bits(machInst, 24, 23) << 1) |
                                     bits(machInst, 14);
                     uint8_t ff = bits(machInst, 13);
-                    if (ff) {
-                        return new Unknown64(machInst);
-                    }
                     return decodeSveGatherLoadSVInsts(
                             dtype, machInst, zt, pg, rn, zm,
                             false, false, false, true, ff);