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author | Gabe Black <gblack@eecs.umich.edu> | 2010-12-09 14:45:17 -0800 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2010-12-09 14:45:17 -0800 |
commit | 2ff3e6b399796a182b3c9cb68f021d1f533356e4 (patch) | |
tree | 157f0930a9047292cf0d0a2e64de8425b23559ed /src/arch/arm/isa/insts/branch.isa | |
parent | 24c5b5925d0bc724a9c6f3f4582def33e113ccf0 (diff) | |
download | gem5-2ff3e6b399796a182b3c9cb68f021d1f533356e4.tar.xz |
ARM: Take advantage of new PCState syntax.
Diffstat (limited to 'src/arch/arm/isa/insts/branch.isa')
-rw-r--r-- | src/arch/arm/isa/insts/branch.isa | 55 |
1 files changed, 18 insertions, 37 deletions
diff --git a/src/arch/arm/isa/insts/branch.isa b/src/arch/arm/isa/insts/branch.isa index 3ff9042e6..d8ea2118e 100644 --- a/src/arch/arm/isa/insts/branch.isa +++ b/src/arch/arm/isa/insts/branch.isa @@ -46,17 +46,14 @@ let {{ # B, BL for (mnem, link) in (("b", False), ("bl", True)): bCode = ''' - ArmISA::PCState pc = PCS; - Addr curPc = pc.instPC(); - pc.instNPC((uint32_t)(curPc + imm)); - PCS = pc; + NPC = (uint32_t)(PC + imm); ''' if (link): bCode += ''' - if (pc.thumb()) - LR = curPc | 1; + if (Thumb) + LR = PC | 1; else - LR = curPc - 4; + LR = PC - 4; ''' bIop = InstObjParams(mnem, mnem.capitalize(), "BranchImmCond", @@ -68,12 +65,9 @@ let {{ # BX, BLX blxCode = ''' - ArmISA::PCState pc = PCS; - Addr curPc M5_VAR_USED = pc.instPC(); %(link)s // Switch modes %(branch)s - PCS = pc; ''' blxList = (("blx", True, True), @@ -85,8 +79,8 @@ let {{ if imm: Name += "Imm" # Since we're switching ISAs, the target ISA will be the opposite - # of the current ISA. pc.thumb() is whether the target is ARM. - newPC = '(pc.thumb() ? (roundDown(curPc, 4) + imm) : (curPc + imm))' + # of the current ISA. Thumb is whether the target is ARM. + newPC = '(Thumb ? (roundDown(PC, 4) + imm) : (PC + imm))' base = "BranchImmCond" declare = BranchImmCondDeclare constructor = BranchImmCondConstructor @@ -101,28 +95,28 @@ let {{ // The immediate version of the blx thumb instruction // is 32 bits wide, but "next pc" doesn't reflect that // so we don't want to substract 2 from it at this point - if (pc.thumb()) - LR = curPc | 1; + if (Thumb) + LR = PC | 1; else - LR = curPc - 4; + LR = PC - 4; ''' elif link: linkStr = ''' - if (pc.thumb()) - LR = (curPc - 2) | 1; + if (Thumb) + LR = (PC - 2) | 1; else - LR = curPc - 4; + LR = PC - 4; ''' else: linkStr = "" if imm and link: #blx with imm branchStr = ''' - pc.nextThumb(!pc.thumb()); - pc.instNPC(%(newPC)s); + NextThumb = !Thumb; + NPC = %(newPC)s; ''' else: - branchStr = "pc.instIWNPC(%(newPC)s);" + branchStr = "IWNPC = %(newPC)s;" branchStr = branchStr % { "newPC" : newPC } code = blxCode % {"link": linkStr, @@ -139,12 +133,7 @@ let {{ #CBNZ, CBZ. These are always unconditional as far as predicates for (mnem, test) in (("cbz", "=="), ("cbnz", "!=")): - code = ''' - ArmISA::PCState pc = PCS; - Addr curPc = pc.instPC(); - pc.instNPC((uint32_t)(curPc + imm)); - PCS = pc; - ''' + code = 'NPC = (uint32_t)(PC + imm);\n' predTest = "Op1 %(test)s 0" % {"test": test} iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg", {"code": code, "predicate_test": predTest}) @@ -161,11 +150,7 @@ let {{ ArmISA::TLB::MustBeOne; EA = Op1 + Op2 * 2 ''' - accCode = ''' - ArmISA::PCState pc = PCS; - pc.instNPC(pc.instPC() + 2 * (Mem.uh)); - PCS = pc; - ''' + accCode = 'NPC = PC + 2 * (Mem.uh);\n' mnem = "tbh" else: eaCode = ''' @@ -174,11 +159,7 @@ let {{ ArmISA::TLB::MustBeOne; EA = Op1 + Op2 ''' - accCode = ''' - ArmISA::PCState pc = PCS; - pc.instNPC(pc.instPC() + 2 * (Mem.ub)); - PCS = pc; - ''' + accCode = 'NPC = PC + 2 * (Mem.ub)' mnem = "tbb" iop = InstObjParams(mnem, mnem.capitalize(), "BranchRegReg", {'ea_code': eaCode, |