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| author | Gene Wu <Gene.Wu@arm.com> | 2010-08-23 11:18:41 -0500 |
|---|---|---|
| committer | Gene Wu <Gene.Wu@arm.com> | 2010-08-23 11:18:41 -0500 |
| commit | 66bcbec96e9bb9619b306a281cb18e2b4cea91c5 (patch) | |
| tree | 7cd3bdd69fb3fd19c59bcb1879491334be421d41 /src/arch/arm/isa/insts/branch.isa | |
| parent | ad2c3b008dbc0496bdf4d80c93275e0bbebbb4fb (diff) | |
| download | gem5-66bcbec96e9bb9619b306a281cb18e2b4cea91c5.tar.xz | |
ARM: BX instruction can be contitional if last instruction in a IT block
Branches are allowed to be the last instuction in an IT block. Before it was
assumed that they could not. So Branches in thumb2 were Uncond.
Diffstat (limited to 'src/arch/arm/isa/insts/branch.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/branch.isa | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/isa/insts/branch.isa b/src/arch/arm/isa/insts/branch.isa index 089a2e7d9..98e751e1a 100644 --- a/src/arch/arm/isa/insts/branch.isa +++ b/src/arch/arm/isa/insts/branch.isa @@ -87,9 +87,9 @@ let {{ # Since we're switching ISAs, the target ISA will be the opposite # of the current ISA. !arm is whether the target is ARM. newPC = '(!arm ? (roundDown(curPc, 4) + imm) : (curPc + imm))' - base = "BranchImm" - declare = BranchImmDeclare - constructor = BranchImmConstructor + base = "BranchImmCond" + declare = BranchImmCondDeclare + constructor = BranchImmCondConstructor else: Name += "Reg" newPC = 'Op1' |