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authorAli Saidi <Ali.Saidi@ARM.com>2011-04-04 11:42:27 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2011-04-04 11:42:27 -0500
commitbe096f91b94ded36f43dd7d547a5671f99a264b1 (patch)
tree85442361558d1123c441538a173dabc9a3fa0a6c /src/arch/arm/isa/insts/branch.isa
parent55920a5ca73ded58762f1b7ae25c8cfe8c9e407d (diff)
downloadgem5-be096f91b94ded36f43dd7d547a5671f99a264b1.tar.xz
ARM: Tag appropriate instructions as IsReturn
Diffstat (limited to 'src/arch/arm/isa/insts/branch.isa')
-rw-r--r--src/arch/arm/isa/insts/branch.isa6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/arch/arm/isa/insts/branch.isa b/src/arch/arm/isa/insts/branch.isa
index 84b9bb720..767c07835 100644
--- a/src/arch/arm/isa/insts/branch.isa
+++ b/src/arch/arm/isa/insts/branch.isa
@@ -81,6 +81,7 @@ let {{
for (mnem, imm, link) in blxList:
Name = mnem.capitalize()
+ isRasPop = 0
if imm:
Name += "Imm"
# Since we're switching ISAs, the target ISA will be the opposite
@@ -123,7 +124,7 @@ let {{
instFlags += ["IsCall"]
else:
linkStr = ""
- instFlags += ["IsReturn"]
+ isRasPop = "op1 == INTREG_LR"
if imm and link: #blx with imm
branchStr = '''
@@ -141,7 +142,8 @@ let {{
"branch": branchStr}
blxIop = InstObjParams(mnem, Name, base,
{"code": code, "brTgtCode" : br_tgt_code,
- "predicate_test": predicateTest}, instFlags)
+ "predicate_test": predicateTest,
+ "is_ras_pop" : isRasPop }, instFlags)
header_output += declare.subst(blxIop)
decoder_output += constructor.subst(blxIop)
exec_output += PredOpExecute.subst(blxIop)