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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:02 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:02 -0500 |
| commit | 05866c82f9eb80db05fb423addcc8563efe1b744 (patch) | |
| tree | dc5d03a1f3021a979705dc66de9598d721812bb4 /src/arch/arm/isa/insts/data.isa | |
| parent | 401165c778108ab22aeeee55c4f4451ca93bcffb (diff) | |
| download | gem5-05866c82f9eb80db05fb423addcc8563efe1b744.tar.xz | |
ARM: Construct the predicate test register for more instruction programatically.
If one of the condition codes isn't being used in the execution we should only
read it if the instruction might be dependent on it. With the preeceding changes
there are several more cases where we should dynamically pick instead of assuming
as we did before.
Diffstat (limited to 'src/arch/arm/isa/insts/data.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/data.isa | 48 |
1 files changed, 22 insertions, 26 deletions
diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa index 94693c8ef..41722914a 100644 --- a/src/arch/arm/isa/insts/data.isa +++ b/src/arch/arm/isa/insts/data.isa @@ -103,8 +103,8 @@ let {{ secondOpRe = re.compile("secondOp") immOp2 = "imm" - regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodesC)" - regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodesC)" + regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, OptShiftRmCondCodesC)" + regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, 0)" def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \ buildCc = True, buildNonCc = True, instFlags = []): @@ -125,12 +125,12 @@ let {{ } immCode = secondOpRe.sub(immOp2, code) immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp", - {"code" : immCode, - "predicate_test": predicateTest}, instFlags) + {"code" : immCode, + "predicate_test": pickPredicate(immCode)}, instFlags) immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", - "DataImmOp", - {"code" : immCode + immCcCode, - "predicate_test": condPredicateTest}, instFlags) + "DataImmOp", + {"code" : immCode + immCcCode, + "predicate_test": pickPredicate(immCode + immCcCode)}, instFlags) def subst(iop): global header_output, decoder_output, exec_output @@ -163,15 +163,15 @@ let {{ } regCode = secondOpRe.sub(regOp2, code) regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp", - {"code" : regCode, "is_ras_pop" : isRasPop, - "is_branch" : isBranch, - "predicate_test": predicateTest}, instFlags) + {"code" : regCode, "is_ras_pop" : isRasPop, + "is_branch" : isBranch, + "predicate_test": pickPredicate(regCode)}, instFlags) regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", - "DataRegOp", - {"code" : regCode + regCcCode, - "predicate_test": condPredicateTest, - "is_ras_pop" : isRasPop, - "is_branch" : isBranch}, instFlags) + "DataRegOp", + {"code" : regCode + regCcCode, + "predicate_test": pickPredicate(regCode + regCcCode), + "is_ras_pop" : isRasPop, + "is_branch" : isBranch}, instFlags) def subst(iop): global header_output, decoder_output, exec_output @@ -204,14 +204,14 @@ let {{ } regRegCode = secondOpRe.sub(regRegOp2, code) regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix, - "DataRegRegOp", - {"code" : regRegCode, - "predicate_test": predicateTest}) + "DataRegRegOp", + {"code" : regRegCode, + "predicate_test": pickPredicate(regRegCode)}) regRegIopCc = InstObjParams(mnem + "s", - mnem.capitalize() + suffix + "Cc", - "DataRegRegOp", - {"code" : regRegCode + regRegCcCode, - "predicate_test": condPredicateTest}) + mnem.capitalize() + suffix + "Cc", + "DataRegRegOp", + {"code" : regRegCode + regRegCcCode, + "predicate_test": pickPredicate(regRegCode + regRegCcCode)}) def subst(iop): global header_output, decoder_output, exec_output @@ -241,10 +241,6 @@ let {{ code += ''' SCTLR sctlr = Sctlr; CPSR old_cpsr = Cpsr; - old_cpsr.nz = CondCodesNZ; - old_cpsr.c = CondCodesC; - old_cpsr.v = CondCodesV; - old_cpsr.ge = CondCodesGE; CPSR new_cpsr = cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi); |