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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:17 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:17 -0500 |
| commit | 358fdc2a40e8a455f508532b47e55f3252053805 (patch) | |
| tree | 4641a564de6d0ce42a372be77e35cde55e2c177c /src/arch/arm/isa/insts/data.isa | |
| parent | 596cbe19d4591b900acc022ff5a38fc7ee9a5df7 (diff) | |
| download | gem5-358fdc2a40e8a455f508532b47e55f3252053805.tar.xz | |
ARM: Decode to specialized conditional/unconditional versions of instructions.
This is to avoid condition code based dependences from effectively serializing
instructions when the instruction doesn't actually use them.
Diffstat (limited to 'src/arch/arm/isa/insts/data.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/data.isa | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa index 09019d0f4..5cb9e545b 100644 --- a/src/arch/arm/isa/insts/data.isa +++ b/src/arch/arm/isa/insts/data.isa @@ -129,7 +129,7 @@ let {{ immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", "DataImmOp", {"code" : immCode + immCcCode, - "predicate_test": predicateTest}) + "predicate_test": condPredicateTest}) def subst(iop): global header_output, decoder_output, exec_output @@ -166,7 +166,7 @@ let {{ regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", "DataRegOp", {"code" : regCode + regCcCode, - "predicate_test": predicateTest}) + "predicate_test": condPredicateTest}) def subst(iop): global header_output, decoder_output, exec_output @@ -206,7 +206,7 @@ let {{ mnem.capitalize() + suffix + "Cc", "DataRegRegOp", {"code" : regRegCode + regRegCcCode, - "predicate_test": predicateTest}) + "predicate_test": condPredicateTest}) def subst(iop): global header_output, decoder_output, exec_output |