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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:28 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:28 -0500 |
| commit | a679cd917ac4775979e23594de52f1bca407c08c (patch) | |
| tree | d48bb74b729d2e11e62e1db9a4fb860b70ddd1b3 /src/arch/arm/isa/insts/data.isa | |
| parent | ac650199eeb62bf05fec11a4f2d7666cbd31331c (diff) | |
| download | gem5-a679cd917ac4775979e23594de52f1bca407c08c.tar.xz | |
ARM: Cleanup implementation of ITSTATE and put important code in PCState.
Consolidate all code to handle ITSTATE in the PCState object rather than
touching a variety of structures/objects.
Diffstat (limited to 'src/arch/arm/isa/insts/data.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/data.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa index 9af81b465..e8012ff89 100644 --- a/src/arch/arm/isa/insts/data.isa +++ b/src/arch/arm/isa/insts/data.isa @@ -245,7 +245,7 @@ let {{ CondCodes = CondCodesMask & newCpsr; NextThumb = ((CPSR)newCpsr).t; NextJazelle = ((CPSR)newCpsr).j; - ForcedItState = ((((CPSR)newCpsr).it2 << 2) & 0xFC) + NextItState = ((((CPSR)newCpsr).it2 << 2) & 0xFC) | (((CPSR)newCpsr).it1 & 0x3); ''' buildImmDataInst(mnem + 's', code, flagType, |