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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-10-09 14:53:38 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-11-05 16:31:57 +0000 |
| commit | 76b10e2b4abf36e441707e7e075ade75b11ab667 (patch) | |
| tree | b54452fdeb47c20de2da79c283cb57f86421d946 /src/arch/arm/isa/insts/data64.isa | |
| parent | 75a127e8ba8885c7112fa92de5d81fa024981280 (diff) | |
| download | gem5-76b10e2b4abf36e441707e7e075ade75b11ab667.tar.xz | |
arch-arm: Annotate original address in CMOs
This is needed when a CMO triggers an exception (e.g. DataAbort) In that
case the faulting address should be the one encoded in the instruction
rather than the cacheline address:
According to armarm:
If a memory fault that sets FAR_EL1 is generated from a data cache
maintenance or other DC instruction, FAR_EL1[63:0] holds the address
specified in the register argument of the instruction.
Change-Id: I6d0dadbef6e70db57438b01a76c5def3bdd2d974
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22443
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/isa/insts/data64.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/data64.isa | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa index fcce0112a..75d47925f 100644 --- a/src/arch/arm/isa/insts/data64.isa +++ b/src/arch/arm/isa/insts/data64.isa @@ -412,9 +412,10 @@ let {{ # Cache maintenance fault annotation # The DC ZVA instruction is not classified as a cache maintenance - # instruction, and therefore we shouldn't annotate it + # instruction, and therefore we shouldn't annotate it. cachem_fa = ''' fault->annotate(ArmFault::CM, 1); + fault->annotate(ArmFault::OFA, faultAddr); ''' msrdccvau_ea_code = msr_check_code @@ -422,6 +423,7 @@ let {{ Request::Flags memAccessFlags = Request::CLEAN | Request::DST_POU | ArmISA::TLB::MustBeOne; EA = XBase; + faultAddr = EA; System *sys = xc->tcBase()->getSystemPtr(); Addr op_size = sys->cacheLineSize(); EA &= ~(op_size - 1); @@ -446,6 +448,7 @@ let {{ Request::Flags memAccessFlags = Request::CLEAN | Request::DST_POC | ArmISA::TLB::MustBeOne; EA = XBase; + faultAddr = EA; System *sys = xc->tcBase()->getSystemPtr(); Addr op_size = sys->cacheLineSize(); EA &= ~(op_size - 1); @@ -470,6 +473,7 @@ let {{ Request::Flags memAccessFlags = Request::CLEAN | Request::INVALIDATE | Request::DST_POC | ArmISA::TLB::MustBeOne; EA = XBase; + faultAddr = EA; System *sys = xc->tcBase()->getSystemPtr(); Addr op_size = sys->cacheLineSize(); EA &= ~(op_size - 1); @@ -494,6 +498,7 @@ let {{ Request::Flags memAccessFlags = Request::INVALIDATE | Request::DST_POC | ArmISA::TLB::MustBeOne; EA = XBase; + faultAddr = EA; HCR hcr = Hcr64; SCR scr = Scr64; if (el == EL1 && ArmSystem::haveVirtualization(xc->tcBase()) && |