diff options
| author | Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> | 2017-04-05 13:14:34 -0500 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
| commit | a473b5a6eb269cc303ecfb5e5643d891a5d255d9 (patch) | |
| tree | 4fde47e5c62c566f81d13f6e90ad98cca781ff6e /src/arch/arm/isa/insts/data64.isa | |
| parent | 43d833246fcfe092a0c08dde1fdf7e3d409d1af9 (diff) | |
| download | gem5-a473b5a6eb269cc303ecfb5e5643d891a5d255d9.tar.xz | |
cpu: Simplify the rename interface and use RegId
With the hierarchical RegId there are a lot of functions that are
redundant now.
The idea behind the simplification is that instead of having the regId,
telling which kind of register read/write/rename/lookup/etc. and then
the function panic_if'ing if the regId is not of the appropriate type,
we provide an interface that decides what kind of register to read
depending on the register type of the given regId.
Change-Id: I7d52e9e21fc01205ae365d86921a4ceb67a57178
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2702
Diffstat (limited to 'src/arch/arm/isa/insts/data64.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/data64.isa | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa index d60dc60f1..48fc87ccb 100644 --- a/src/arch/arm/isa/insts/data64.isa +++ b/src/arch/arm/isa/insts/data64.isa @@ -328,7 +328,7 @@ let {{ buildDataXImmInst("mrs", ''' MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()-> - flattenMiscIndex(op1); + flattenRegId(RegId(MiscRegClass, op1)).index(); CPSR cpsr = Cpsr; ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; %s @@ -346,7 +346,7 @@ let {{ buildDataXImmInst("msr", ''' MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()-> - flattenMiscIndex(dest); + flattenRegId(RegId(MiscRegClass, dest)).index(); CPSR cpsr = Cpsr; ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; %s @@ -362,7 +362,8 @@ let {{ ''') msrdczva_ea_code = ''' - MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest); + MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->flattenRegId( + RegId(MiscRegClass, dest)).index(); CPSR cpsr = Cpsr; ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; ''' @@ -391,7 +392,8 @@ let {{ buildDataXImmInst("msrSP", ''' if (!canWriteAArch64SysReg( - (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest), + (MiscRegIndex) xc->tcBase()->flattenRegId( + RegId(MiscRegClass, dest)).index(), Scr64, Cpsr, xc->tcBase())) { return std::make_shared<UndefinedInstruction>(machInst, false, mnemonic); @@ -401,7 +403,8 @@ let {{ buildDataXImmInst("msrDAIFSet", ''' if (!canWriteAArch64SysReg( - (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest), + (MiscRegIndex) xc->tcBase()->flattenRegId( + RegId(MiscRegClass, dest)).index(), Scr64, Cpsr, xc->tcBase())) { return std::make_shared<UndefinedInstruction>( machInst, 0, EC_TRAPPED_MSR_MRS_64, @@ -414,7 +417,8 @@ let {{ buildDataXImmInst("msrDAIFClr", ''' if (!canWriteAArch64SysReg( - (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest), + (MiscRegIndex) xc->tcBase()->flattenRegId( + RegId(MiscRegClass, dest)).index(), Scr64, Cpsr, xc->tcBase())) { return std::make_shared<UndefinedInstruction>( machInst, 0, EC_TRAPPED_MSR_MRS_64, |