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author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:11 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:11 -0500 |
commit | f3e65c2de285d185936674375a353d71e547d2eb (patch) | |
tree | 3fa0b5466d92523c043b2506a46c983e124c27b7 /src/arch/arm/isa/insts/div.isa | |
parent | 5943f0fc84ba51d8341a97437b798225fd36da56 (diff) | |
download | gem5-f3e65c2de285d185936674375a353d71e547d2eb.tar.xz |
ARM: Implement the sdiv instruction.
Diffstat (limited to 'src/arch/arm/isa/insts/div.isa')
-rw-r--r-- | src/arch/arm/isa/insts/div.isa | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/div.isa b/src/arch/arm/isa/insts/div.isa new file mode 100644 index 000000000..b3bd19cdb --- /dev/null +++ b/src/arch/arm/isa/insts/div.isa @@ -0,0 +1,56 @@ +// -*- mode:c++ -*- + +// Copyright (c) 2010 ARM Limited +// All rights reserved +// +// The license below extends only to copyright in the software and shall +// not be construed as granting a license to any other intellectual +// property including but not limited to intellectual property relating +// to a hardware implementation of the functionality of the software +// licensed hereunder. You may use the software subject to the license +// terms below provided that you ensure that this notice is replicated +// unmodified and in its entirety in all distributions of the software, +// modified or unmodified, in source code or in binary form. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Gabe Black + +let {{ + sdivCode = ''' + if (Op2.sw == 0) { + Dest.sw = 0; + } else if (Op1.sw == INT_MIN && Op2.sw == -1) { + Dest.sw = INT_MIN; + } else { + Dest.sw = Op1.sw / Op2.sw; + } + ''' + sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp", + { "code": sdivCode, + "predicate_test": predicateTest }, []) + header_output = RegRegRegOpDeclare.subst(sdivIop) + decoder_output = RegRegRegOpConstructor.subst(sdivIop) + exec_output = PredOpExecute.subst(sdivIop) +}}; |