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| author | Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> | 2010-11-15 14:04:04 -0600 |
|---|---|---|
| committer | Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> | 2010-11-15 14:04:04 -0600 |
| commit | 005892719047c3b4b383d9aeeeb481039518f661 (patch) | |
| tree | b2d967a9ffea13f73e092804ae141d9520ff109c /src/arch/arm/isa/insts/div.isa | |
| parent | 2a3cefe15115a094eadd74a659a2f919a83ac6a4 (diff) | |
| download | gem5-005892719047c3b4b383d9aeeeb481039518f661.tar.xz | |
CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
Diffstat (limited to 'src/arch/arm/isa/insts/div.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/div.isa | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/arch/arm/isa/insts/div.isa b/src/arch/arm/isa/insts/div.isa index 302beb6b3..d736f9230 100644 --- a/src/arch/arm/isa/insts/div.isa +++ b/src/arch/arm/isa/insts/div.isa @@ -56,7 +56,8 @@ let {{ ''' sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp", { "code": sdivCode, - "predicate_test": predicateTest }, []) + "predicate_test": predicateTest, + "op_class": "IntDivOp"}, []) header_output = RegRegRegOpDeclare.subst(sdivIop) decoder_output = RegRegRegOpConstructor.subst(sdivIop) exec_output = PredOpExecute.subst(sdivIop) @@ -77,7 +78,8 @@ let {{ ''' udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp", { "code": udivCode, - "predicate_test": predicateTest }, []) + "predicate_test": predicateTest, + "op_class": "IntDivOp"}, []) header_output += RegRegRegOpDeclare.subst(udivIop) decoder_output += RegRegRegOpConstructor.subst(udivIop) exec_output += PredOpExecute.subst(udivIop) |