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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:11 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:11 -0500 |
| commit | c3bf29bbeabdd3510a2e3c81c653c2931ad26e64 (patch) | |
| tree | e3e1127150c71a880712e202690e185ddc201c5e /src/arch/arm/isa/insts/div.isa | |
| parent | f3e65c2de285d185936674375a353d71e547d2eb (diff) | |
| download | gem5-c3bf29bbeabdd3510a2e3c81c653c2931ad26e64.tar.xz | |
ARM: Implement the udiv instruction.
Diffstat (limited to 'src/arch/arm/isa/insts/div.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/div.isa | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/div.isa b/src/arch/arm/isa/insts/div.isa index b3bd19cdb..b240e2967 100644 --- a/src/arch/arm/isa/insts/div.isa +++ b/src/arch/arm/isa/insts/div.isa @@ -53,4 +53,18 @@ let {{ header_output = RegRegRegOpDeclare.subst(sdivIop) decoder_output = RegRegRegOpConstructor.subst(sdivIop) exec_output = PredOpExecute.subst(sdivIop) + + udivCode = ''' + if (Op2.uw == 0) { + Dest.uw = 0; + } else { + Dest.uw = Op1.uw / Op2.uw; + } + ''' + udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp", + { "code": udivCode, + "predicate_test": predicateTest }, []) + header_output += RegRegRegOpDeclare.subst(udivIop) + decoder_output += RegRegRegOpConstructor.subst(udivIop) + exec_output += PredOpExecute.subst(udivIop) }}; |