diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-08-25 19:10:43 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-08-25 19:10:43 -0500 |
| commit | edca5f7da6bad677dfc1ea69fff904554181cc17 (patch) | |
| tree | 19e1656c6267c6677944160d10ea1a229f409b94 /src/arch/arm/isa/insts/fp.isa | |
| parent | e6d3fe8a0c02e0692444399e63e6c5ce6c3abd17 (diff) | |
| download | gem5-edca5f7da6bad677dfc1ea69fff904554181cc17.tar.xz | |
ARM: Make VMSR, RFE PC/LR etc non speculative, and serializing
Diffstat (limited to 'src/arch/arm/isa/insts/fp.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/fp.isa | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa index 6ba4ac3bf..6d91ebf53 100644 --- a/src/arch/arm/isa/insts/fp.isa +++ b/src/arch/arm/isa/insts/fp.isa @@ -194,7 +194,8 @@ let {{ vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp", { "code": vmsrEnabledCheckCode + \ "MiscDest = Op1;", - "predicate_test": predicateTest }, []) + "predicate_test": predicateTest }, + ["IsSerializeAfter","IsNonSpeculative"]) header_output += FpRegRegOpDeclare.subst(vmsrIop); decoder_output += FpRegRegOpConstructor.subst(vmsrIop); exec_output += PredOpExecute.subst(vmsrIop); |