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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
| commit | e097c4fb188fafc9cd2253500ab2d056da886c9c (patch) | |
| tree | badbc1cc2849c52a77a211d805af04903223d469 /src/arch/arm/isa/insts/ldr.isa | |
| parent | 2178859b76bb13b1d225fc4dffa04d43d2db2e14 (diff) | |
| download | gem5-e097c4fb188fafc9cd2253500ab2d056da886c9c.tar.xz | |
ARM: Remove the saturating (Q) condition code from the renamed register.
Move the saturating bit (which is also saturating) from the renamed register
that holds the flags to the CPSR miscreg and adds a allows setting it in a
similar way to the FP saturating registers. This removes a dependency in
instructions that don't write, but need to preserve the Q bit.
Diffstat (limited to 'src/arch/arm/isa/insts/ldr.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/ldr.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa index bf8034a9e..9211983d4 100644 --- a/src/arch/arm/isa/insts/ldr.isa +++ b/src/arch/arm/isa/insts/ldr.isa @@ -106,7 +106,7 @@ let {{ wbDiff = 8 accCode = ''' CPSR cpsr = Cpsr; - URc = cpsr | CondCodesF | CondCodesQ | CondCodesGE; + URc = cpsr | CondCodesF | CondCodesGE; URa = cSwap<uint32_t>(Mem.ud, cpsr.e); URb = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e); ''' |