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| author | Ali Saidi <Ali.Saidi@arm.com> | 2010-08-23 11:18:40 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@arm.com> | 2010-08-23 11:18:40 -0500 |
| commit | 0c434b7f5650be8e742199e2d1efb5d642e210c5 (patch) | |
| tree | 4747cd22b02f2edb3ac5de02b28f29c7e8251e26 /src/arch/arm/isa/insts/ldr.isa | |
| parent | 5148c693d84062af857b5b8663e44434dba2b894 (diff) | |
| download | gem5-0c434b7f5650be8e742199e2d1efb5d642e210c5.tar.xz | |
ARM: Exclusive accesses must be double word aligned
Diffstat (limited to 'src/arch/arm/isa/insts/ldr.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/ldr.isa | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa index cc6b6351b..6919bbca4 100644 --- a/src/arch/arm/isa/insts/ldr.isa +++ b/src/arch/arm/isa/insts/ldr.isa @@ -206,7 +206,9 @@ let {{ # Add memory request flags where necessary if self.flavor == "exclusive": self.memFlags.append("Request::LLSC") - self.memFlags.append("ArmISA::TLB::AlignWord") + self.memFlags.append("ArmISA::TLB::AlignDoubleWord") + else: + self.memFlags.append("ArmISA::TLB::AlignWord") # Disambiguate the class name for different flavors of loads if self.flavor != "normal": |