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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:04 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:04 -0500
commit2419903dc0c100b1eb3111a5e0fc9b186c79e6ed (patch)
tree38609c5e76f8a81cbf0631ab9df28918f5d98bbd /src/arch/arm/isa/insts/ldr.isa
parent28227440a7645d2f486c0c1f79ef22514aeaa4c8 (diff)
downloadgem5-2419903dc0c100b1eb3111a5e0fc9b186c79e6ed.tar.xz
ARM: Make ldrs into the PC and ldm exception return do interworking branches.
Diffstat (limited to 'src/arch/arm/isa/insts/ldr.isa')
-rw-r--r--src/arch/arm/isa/insts/ldr.isa4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index 86cb76383..b058ba73c 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -90,7 +90,7 @@ let {{
eaCode += offset
eaCode += ";"
- accCode = "Dest = Mem%s;\n" % buildMemSuffix(sign, size)
+ accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
if writeback:
accCode += "Base = Base %s;\n" % offset
base = buildMemBase("MemoryImm", post, writeback)
@@ -115,7 +115,7 @@ let {{
eaCode += offset
eaCode += ";"
- accCode = "Dest = Mem%s;\n" % buildMemSuffix(sign, size)
+ accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
if writeback:
accCode += "Base = Base %s;\n" % offset
base = buildMemBase("MemoryReg", post, writeback)